AM79C971KCW AMD [Advanced Micro Devices], AM79C971KCW Datasheet - Page 183
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AM79C971KCW
Manufacturer Part Number
AM79C971KCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C971KCW.pdf
(265 pages)
- Current page: 183 of 265
- Download datasheet (3Mb)
Mode
The mode register field of the initialization block is cop-
ied into CSR15 and interpreted according to the de-
scription of CSR15.
Receive Descriptors
When SWSTYLE (BCR20, bits 7-0) is set to 0, then the
software structures are defined to be 16 bits wide, and
receive descriptors look like Table 46 (CRDA = Current
Receive Descriptor Address).
When SWSTYLE (BCR 20, bits 7-0) is set to 2, then the
software structures are defined to be 32 bits wide, and
receive descriptors look like Table 47 (CRDA = Current
Receive Descriptor Address).
When SWSTYLE (BCR 20, bits 7-0) is set to 3, then the
software structures are defined to be 32 bits wide, and
receive descriptors look like Table 48 (CRDA = Current
Receive Descriptor Address).
CRDA+0Ch
CRDA+0Ch
CRDA+00h
CRDA+04h OWN ERR
CRDA+08h RES
CRDA+00h RES
CRDA+04h OWN ERR
CRDA+08h
Address
Address
CRDA+00h
CRDA+02h
CRDA+04h
CRDA+06h
Address
31
31
OWN
15
30
30
1
0
FRA
FRA
29
29
M
M
ERR
14
1
0
OFL
OFL
Table 46. Receive Descriptor (SWSTYLE = 0)
28
28
Table 48. Receive Descriptor (SWSTYLE = 3)
Table 47. Receive Descriptor (SWSTYLE = 2
O
O
FRAM
CRC
CRC
27
27
13
1
0
P R E L I M I N A R Y
BUF
BUF
26
26
F
F
OFLO
12
1
0
STP ENP BPE
STP ENP BPE
25
25
Am79C971
RFRTAG[14:0]
RFRTAG[14:0]
USER SPACE
USER SPACE
CRC
RBADR[31:0]
RBADR[31:0]
24
24
11
RBADR[15:0]
RMD0
Bit
31-0
RMD1
Bit
31
.
23
23
BUFF
RBADR
OWN
10
Name
Name
PAM
PAM
22
22
STP
LAFM
LAFM
9
21
21
MCNT
Receive Buffer address. This field
contains the address of the re-
ceive buffer that is associated
with this descriptor.
This bit indicates whether the de-
scriptor entry is owned by the
host (OWN = 0) or by the
Am79C971 controller (OWN = 1).
The Am79C971 controller clears
the OWN bit after filling the buffer
that the descriptor points to. The
host sets the OWN bit after emp-
tying the buffer
BCNT
Description
Description
BAM
BAM
ENP
20
20
8
19-16
19-16
RES
RES
RBADR[23:16]
15-12
15-12
1111
0000
0000
1111
7-0
MCNT
MCNT
BCNT
BCNT
11-0
11-0
183
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