AM79C971KCW AMD [Advanced Micro Devices], AM79C971KCW Datasheet - Page 261

• Manufacturer Part Number: AM79C971KCW
• Manufacturer: AMD [Advanced Micro Devices]

CSR43
CSR44
CSR45
CSR46
CSR47
CSR48
CSR49
CSR5
CSR58
CSR6
CSR60
CSR61
CSR62
CSR63
CSR64
CSR65
CSR66
CSR67
CSR7
CSR72
CSR74
CSR76
CSR78
CSR8
CSR80
CSR82
CSR84
Current Transmit Byte Count
Current Transmit Status
Next Receive Byte Count
Next Receive Status
Transmit Poll Time Counter
Transmit Polling Interval
Receive Poll Time Counter
Receive Polling Interval
Extended Control and Interrupt 1
Software Style
RX/TX Descriptor Table Length
Previous Transmit Descriptor Address
Previous Transmit Descriptor Address
Previous Transmit Byte Count
Previous Transmit Status
Next Transmit Buffer Address Lower
Next Transmit Buffer Address Upper
Next Transmit Byte Count
Next Transmit Status
Extended Control and Interrupt 2
Receive Ring Counter
Transmit Ring Counter
Receive Ring Length
Transmit Ring Length
Logical Address Filter 0
DMA Transfer Counter and FIFO Threshold
Transmit Descriptor Address Pointer Lower
Control
Lower
Upper
137
137
137
137
137
137
138
138
123
139
125
140
140
141
141
141
141
141
141
126
142
142
142
142
129
142
144
D
Data Decoding
Data Registers, Other
DC Characteristics, Over Commercial
Operating Ranges Unless Otherwise
Specified
Decoupling/Bypass Capacitors
Descriptor
Detailed Functions
Differential Input Termination
Direct Access to the Interface
Direct Flash Access
Direct SRAM Access
Disconnect
Distinctive Characteristics
DMA Transfers
E
EEPROM Interface
EEPROM MAP
EEPROM-Programmable Registers
Expansion Bus Interface
Expansion ROM - Boot Device Access
Expansion ROM Transfers
External Address Detection Interface
External Address Detection Interface,
EEPROM Interface
CSR86
CSR88
CSR89
CSR9
CSR92
DMA Transfers
Rings
Of Burst Transfer
Without Data Transfer
FIFO
AMD Flash Programming
Direct Flash Access
Direct SRAM Access
Expansion ROM - Boot Device Access
External SRAM Configuration
Frequency Demands for Network Operation 94
Low Latency Receive Configuration
No SRAM Configuration
SRAM Accesses
SRAM Interface Bandwidth Requirements
Internal PHY
Receive Frame Tagging
DMA Address Register Lower
Buffer Byte Counter
Chip ID Register Lower
Chip ID Register Upper
Logical Address Filter 1
Ring Length Conversion
22, 94
22, 84
145
145
145
146
129
146
100
200
B-1
72
47
54
30
72
92
92
95
86
92
34
41
50
95
95
89
86
92
84
90
93
94
84
33
81
81
83
26
1
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