AM79C971KCW AMD [Advanced Micro Devices], AM79C971KCW Datasheet - Page 263
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AM79C971KCW
Manufacturer Part Number
AM79C971KCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C971KCW.pdf
(265 pages)
- Current page: 263 of 265
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MENDEC Transmit Path
MII
MII, See Media Independent Interface
Miscellaneous Loopback Features
Mode
Modes
N
Network Interfaces, Basic Functions
No SRAM Configuration, AMD Flash
Programming
Non-Burst FIFO DMA Transfers
O
Operating Ranges
Operating Ranges, DC Characteristics
Operation
Ordering Information
Outline, LAPP Flow
P
PADR
Parity Error Response
PCI (Peripheral Component Interconnect)
Physical Dimensions
MII Network Port Manager
MII Network Status Interface
MII Receive Interface
MII Transmit Interface
Transmit and Receive Message Data
AUI
GPSI
T-MAU
Automatic Pad Generation
Transmit Exception Conditions
Transmit FCS Generation
Transmit Function Programming
Command Register
Expansion ROM Base Address Register
Header Type Register
Interrupt Line Register
Interrupt Pin Register
Latency Timer Register
MAX_LAT Register
Memory Mapped I/O Base Address
MIN_GNT Register
PCI I/O Base Address Register
Programming Interface Register
Revision ID Register
Status Register
Sub-Class Register
Subsystem ID Register
Subsystem Vendor ID Register
Encapsulation
Register
35, 43
183
200
200
182
108
113
111
114
114
111
114
112
114
111
111
111
109
111
113
113
229
D-1
79
77
76
76
60
70
60
69
72
75
69
29
92
50
64
65
64
63
4
Pin Designations
PLL Tracking
Polarity Detection and Reversal
Power Savings Modes
Power Supply Pins
Preemption
R
Receive
Receive Descriptors
Receiver Path, Manchester Encoder/Decoder
Recommendation for Power and Ground
Decoupling
Register Programming Summary
Related AMD Products
Reset
RMD0
RMD1
RMD2
RMD3
S
Signal Quality Error Test Function
Slave
Slave I/O Transfers
Sleep Mode
Listed By Driver Type
Listed by Group
Listed by Pin Number
Magic Packet
Sleep
During Non-Burst Transaction
Descriptor Table Entry
Exception Conditions
FCS Checking
Operation
RMD0
RMD1
RMD2
RMD3
Am79C971 Bus Configuration Registers
Am79C971 Control and Status Registers
Am79C971Programmable Registers
H_Reset
RLEN and TLEN
STOP
Bus Interface Unit
Configuration Transfers
Slave Cycle Termination
Address Matching
Automatic Pad Stripping
Exception Conditions
FCS Checking
Function Programming
Disconnect of Burst Transfer
Parity Error Response
183
183
183
185
186
196
198
196
196
102
102
181
102
183
183
185
186
B-1
28
58
66
67
68
68
66
10
30
30
34
35
17
15
13
71
73
97
98
97
42
68
68
71
74
30
97
I-5
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