AM79C971KCW AMD [Advanced Micro Devices], AM79C971KCW Datasheet - Page 95
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AM79C971KCW
Manufacturer Part Number
AM79C971KCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C971KCW.pdf
(265 pages)
- Current page: 95 of 265
- Download datasheet (3Mb)
If the user wishes to modify any of the configuration bits
that are contained in the EEPROM, then the seven
command, data and status bits of BCR19 can be used
to write to the EEPROM. After writing to the EEPROM,
the host should set the PREAD bit of BCR19. This
action forces an Am79C971 controller reread of the
EEPROM so that the new EEPROM contents will be
loaded into the EEPROM-programmable registers on
board the Am79C971 controller. (The EEPROM-pro-
grammable registers may also be reprogrammed di-
rectly, but only information that is stored in the
EEPROM will be preserved at system power-down.)
When the PREAD bit of BCR19 is set, it will cause the
Am79C971 controller to ignore further accesses to the
Am79C971 configuration space, the Expansion ROM,
or any I/O resource until the completion of the EE-
PROM read operation. The Am79C971 controller will
terminate these access attempts with the assertion of
DEVSEL and STOP while TRDY is not asserted, sig-
naling to the initiator to disconnect and retry the access
at a later time.
EEPROM Auto-Detection
The Am79C971 controller uses the EESK/LED1/SFBD
pin to determine if an EEPROM is present in the sys-
tem. At the rising edge of CLK during the last clock dur-
ing which RST is asserted, the Am79C971 controller
will sample the value of the EESK/LED1/SFBD pin. If
the sampled value is a 1, then the Am79C971 controller
assumes that an EEPROM is present, and the EE-
PROM read operation begins shortly after the RST pin
is deasserted. If the sampled value of EESK/LED1/
SFBD is a 0, the Am79C971 controller assumes that an
external pulldown device is holding the EESK/LED1/
SFBD pin low, indicating that there is no EEPROM in
the system. Note that if the designer creates a system
that contains an LED circuit on the EESK/LED1/SFBD
pin, but has no EEPROM present, then the EEPROM
auto-detection function will incorrectly conclude that an
EEPROM is present in the system. However, this will
not pose a problem for the Am79C971 controller, since
the checksum verification will fail.
Direct Access to the Interface
The user may directly access the port through the
EEPROM register, BCR19. This register contains bits
that can be used to control the interface pins. By per-
forming an appropriate sequence of accesses to
BCR19, the user can effectively write to and read from
the EEPROM. This feature may be used by a system
configuration utility to program hardware configuration
information into the EEPROM.
Am79C971
EEPROM-Programmable Registers
The following registers contain configuration informa-
tion that will be programmed automatically during the
EEPROM read operation:
If PREAD (BCR19, bit 14) and PVALID (BCR19, bit 15)
are cleared to 0, then the EEPROM read has experi-
enced a failure and the contents of the EEPROM pro-
grammable BCR register will be set to default
H_RESET values. The content of the Address PROM
locations, however, will not be cleared.
Note that accesses to the Address PROM I/O locations
do not directly access the Address EEPROM itself. In-
stead, these accesses are routed to a set of shadow
registers on board the Am79C971 controller that are
loaded with a copy of the EEPROM contents during the
automatic read operation that immediately follows the
H_RESET operation.
EEPROM MAP
The automatic EEPROM read operation will access 32
words (i.e., 64 bytes) of the EEPROM. The format of
the EEPROM contents is shown in Table 14, beginning
with the byte that resides at the lowest EEPROM ad-
dress.
Note that the first bit out of any word location in the EE-
PROM is treated as the MSB of the register being pro-
grammed. For example, the first bit out of EEPROM
word location 09h will be written into BCR4, bit 15; the
second bit out of EEPROM word location 09h will be
written into BCR4, bit 14, etc.
I/O offsets 0h-Fh Address PROM locations
BCR2
BCR4
BCR5
BCR6
BCR7
BCR9
BCR18
BCR22
BCR23
BCR24
BCR25
BCR26
BCR27
BCR32
BCR33
BCR35
Miscellaneous Configuration
LED0 Status
LED1 Status
LED2 Status
LED3 Status
Full-Duplex Control
Burst and Bus Control
PCI Latency
PCI Subsystem Vendor ID
PCI Subsystem ID
SRAM Size
SRAM Boundary
SRAM Interface Control
MII Control and Status
MII Address
PCI Vendor ID
95
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