K9F1G08U0A SAMSUNG [Samsung semiconductor], K9F1G08U0A Datasheet
K9F1G08U0A
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K9F1G08U0A Summary of contents
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Document Title 128M x 8 Bit / 256M x 8 Bit Revision History Revision No History 0.0 1. Initial issue 0.1 1. The tADL(Address to Data Loading Time) is added. - tADL Minimum 100ns (Page 11, 23~26) - tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle at program operation. ...
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... Pin TSOP I ( 0.5 mm pitch) - K9F1G08U0A-VIB0 48 - Pin WSOP I (12X17X0.7mm) - K9F1G08U0A-PCB0/PIB0 48 - Pin TSOP I ( 0.5 mm pitch)- Pb-free Package - K9F1G08U0A-FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F1G08U0A-V,F(WSOPI ) is the same device as K9F1G08U0A-Y,P(TSOP1) except package type. - K9K2G08U1A-ICB0/IIB0 52-ULGA (12X17X0.65mm) 2 FLASH MEMORY PKG Type Only available in MCP ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A PIN CONFIGURATION (TSOP1) K9F1G08X0A-YCB0,PCB0/YIB0,PIB0 X8 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220AF #1 #24 0~8° 0.45~0.75 0.018~0.030 ...
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... Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F1G08U0A-VIB0,FIB0 15.40 ±0.10 #48 #25 17.00 ± ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A PIN CONFIGURATION (ULGA /CE1 4 3 CLE1 PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View 12.00±0.10 #A1 K9K2G08U1A-ICB0/IIB0 /RE1 /RB2 IO7-2 NC IO6-2 IO5-2 Vcc /RE2 Vss IO7-1 IO5-1 ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Figure 1-1. K9F1G08X0A Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE PRE Figure 2-1. K9F1G08X0A Array Organization 64K Pages (=1,024 Blocks) ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Product Introduction The K9F1G08X0A is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. Spare 64 col- umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con- nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations ...
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... Input Low Voltage, All inputs V IL* K9F1G08R0A :I Output High Voltage Level V OH K9F1G08U0A :I Output Low Voltage Level K9F1G08R0A : K9F1G08U0A :I K9F1G08R0A :V Output Low Current(R/B) I (R/B) OL K9F1G08U0A :V NOTE : V can undershoot to -0.4V and V can overshoot Symbol 1.8V DEVICE V -0 2.45 IN/OUT BIAS T STG Ios +0 ...
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... Refer to the attached technical notes for appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed valid block, does not require Error Correction program/erase cycles. Each K9F1G08U0A chip in the K9K2G08U1A has Maximum 20 invalid blocks TEST CONDITION (K9F1G08X0A-XCB0 :TA=0 to 70° ...
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... IR t 100 100 RHW WHR RST 11 FLASH MEMORY Max Unit K9F1G08R0A K9F1G08U0A - - Max Unit K9F1G08R0A K9F1G08U0A µ 100 100 µs 5/10/500 5/10/500 *1 *1 ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A NAND Flash Technical Notes Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig- nificant bit) pages of the block. Random page address programming is prohibited. (64) ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A NOTE I/O Device I/Ox K9F1G08X0A I I/O 7 Command Latch Cycle CLE CE WE ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE I/Ox DATA Data In/Out Col. Add1 ~2112byte A0~ CLS CLH ALS ALH Command ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Input Data Latch Cycle CLE CE t ALS ALE I/Ox DIN 0 Serial Access Cycle after Read t CEA CE t REA I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Status Read Cycle CLE I/Ox t CLR t CLS t CLH CEA t WHR IR* 70h 19 FLASH MEMORY t CHZ RHZ* t REA t OH Status Output ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Read Operation CLE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B t CLR 30h Dout N Row Add1 Row Add2 ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A FLASH MEMORY 21 ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Page Program Operation CLE ALE RE I/Ox Col. Add2 80h Co.l Add1 SerialData Column Address Input Command R/B NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ADL Din Din ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 23 ≈ ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A FLASH MEMORY ≈ ≈ ≈ ≈ ≈ 24 ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A ≈ ≈ FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 25 ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h Row Add1 Row Add2 Row Address R/B Auto Block Erase Erase Command Setup Command t t BERS WB D0h Busy Read Status Command 26 FLASH MEMORY 70h I/O 0 I/O =0 Successful Erase 0 I/O =1 Error in Erase 0 ...
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... Byte rd Page Size, Block Size, Spare Size, Organization,Serial access minimum 4 Byte REA Device 00h ECh Code* Maker Code Device Code Device Code*(2nd Cycle) A1h F1h Same as each K9F1G08U0A FLASH MEMORY 4th cyc.* XXh 4th Cycle* 15h 15h ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A 4th ID Data ITEM Description 1KB Page Size 2KB (w/o redundant area ) Reserved Reserved 64KB Block Size 128KB (w/o redundant area ) 256KB Reserved Redundant Area Size 8 ( byte/512byte Organization x16 50ns/30ns 25ns Serial Access minimum Reserved Reserved FLASH MEMORY I/O7 I/O6 I/O5 I/O4 I/ ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25µ ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 4Cycles Col Add1,2 & Row Add1,2 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a word or consecutive bytes up to 2112 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for main array(1time/512byte) and 4 times for spare array(1time/16byte) ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Figure 9. Random Data Input In a Page R/B I/Ox Address & Data Input 80h Col Add1,2 & Row Add1,2 Data Cache Program Cache Program is an extension of Page Program, which is executed with 2112byte data registers, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory cell ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A NOTE : Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after comple- tion of the previous cycle, which can be expressed as the following formula ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... Device REA ECh Code* Maker code Device code Device Device Code*(2nd Cycle) K9F1G08R0A A1h K9F1G08U0A F1h K9K2G08U1A Same as each K9F1G08U0A RST After Power-up 00h command is latched 34 FLASH MEMORY XXh 4th Cyc.* 4th Cycle* 15h 15h After Reset Waiting for next command ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit IL gets ready for any command sequences as shown in Figure 17 ...
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... K9F1G08R0A K9F1G08U0A K9K2G08U1A Extended Data Out Mode For the EDO mode, the device should hold the data on the system memory bus until the beginning of the next cycle, so that controller could fetch the data at the falling edge. However NAND flash dosen’t support the EDO mode exactly. ...