K9F1G08U0A SAMSUNG [Samsung semiconductor], K9F1G08U0A Datasheet - Page 8

• Manufacturer Part Number: K9F1G08U0A
• Description: 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9F1G08R0A
K9F1G08U0A
Product Introduction
The K9F1G08X0A is a 1056Mbit(1,107,296,256 bit) memory organized as 65,536 rows(pages) by 2112x8 columns. Spare 64 col-
umns are located from column address of 2048~2111. A 2112-byte data register and a 2112-byte cache register are serially con-
nected to each other. Those serially connected registers are connected to memory cell arrays for accommodating data transfer
between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells
that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND
structured strings. A NAND structure consists of 32 cells. Total 1081344 NAND cells reside in a block. The program and read opera-
tions are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 1024 sep-
arately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1G08X0A.
The K9F1G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 128M byte physical space
requires 28 addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 2 cycles of row address, in that
order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase oper-
ation, however, only the two row address cycles are used. Device operations are selected by writing specific commands into the com-
mand register. Table 1 defines the specific commands of the K9F1G08X0A.
The device provides cache program in a block. It is possible to write data into the cache registers while data stored in data registers
are being programmed into memory cells in cache program mode. The program performace may be dramatically improved by cache
program when there are lots of pages of data to be programmed.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and
data-input cycles are removed, system performance for solid-state disk application is significantly increased.
Table 1. Command Sets
NOTE : 1. Random Data Input/Output can be executed in a page.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
Read
Read for Copy Back
Read ID
Reset
Page Program
Cache Program
Copy-Back Program
Block Erase
Random Data Input
Random Data Output
Read Status
2. Cache program and Copy-Back program are supported only with 3.3V device.
Function
*2
*1
*1
K9K2G08U1A
1st. Cycle
00h
00h
90h
FFh
80h
80h
85h
85h
05h
70h
60h
8
2nd. Cycle
D0h
E0h
30h
35h
10h
15h
10h
-
-
-
Acceptable Command during Busy
FLASH MEMORY
O
O