USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet
USB97C201-MN
Related parts for USB97C201-MN
USB97C201-MN Summary of contents
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... LED indicator. 100 Pin TQFP Package (14.0 x 14.0 mm footprint) - 25% smaller body size than other 100 pin TQFP Packages 100 Pin QFP Package ORDERING INFORMATION Order Numbers: USB97C201-MN for 100 pin TQFP package USB97C201-MC for 100 pin QFP package Page 1 PRELIMINARY USB97C201 Rev 1.5 ...
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... OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – USB97C201 Page 2 PRELIMINARY Rev. 03/25/2002 ...
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... Phase 1 (Ø1)..........................................................................................................................49 6.7.3 Phase 2 (Ø2)..........................................................................................................................49 6.7.4 Phase 3 (Ø3)..........................................................................................................................49 6.8 EP2 SRAM Buffer Operation........................................................................................................49 6.9 EP2 Automatic Buffer Operations...............................................................................................50 6.9.1 Receive Auto-Toggle .............................................................................................................50 6.9.2 Transmit Buffer Operation .....................................................................................................51 6.9.3 Automatic Transfer Operation................................................................................................52 7.0 DC PARAMETERS............................................................................................................................................ 54 8.0 AC SPECIFICATIONS....................................................................................................................................... 56 8.1 ATA/ATAPI .....................................................................................................................................56 8.2 USB2.0 Timing ..............................................................................................................................56 9.0 PACKAGING ..................................................................................................................................................... 57 10.0 USB97C201 REVISIONS.............................................................................................................................. 59 SMSC DS – USB97C201 TABLE OF CONTENTS Page 3 PRELIMINARY Rev. 03/25/2002 ...
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... Table 1 - USB97C201 Buffer Type Descriptions ......................................................................................................... 13 Table 2 - MCU Code Memory Map.............................................................................................................................. 14 Table 3 - MCU XData Memory Map ............................................................................................................................ 15 Table 4 - MCU Block Register Summary..................................................................................................................... 16 Table 5 - 8051 Core SFR Register Summary.............................................................................................................. 18 Table 6 - Interrupt 0 Source Register .......................................................................................................................... 19 Table 7 - Interrupt 0 Mask ........................................................................................................................................... 20 Table 8 - Interrupt 1 Source Register .......................................................................................................................... 20 Table 9 - Interrupt 1 Mask ........................................................................................................................................... 21 Table 10 - Device Revision Register ........................................................................................................................... 21 Table 11 - Device Identification Register ...
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... Figure 1 - MCU to EXTERNAL CODE SPACE MAP ................................................................................................... 14 Figure 2 - GPIO MUXING BLOCK DIAGRAM ............................................................................................................. 23 Figure 3 - RECEIVE BUFFER OPERATION ............................................................................................................... 51 Figure 4 - TRANSMIT BUFFER OPERATION............................................................................................................. 52 Figure 5 - AUTOMATIC DATA TRANSFER OPERATION ......................................................................................... 53 Figure 6 - 100 PIN TQFP PACKAGE .......................................................................................................................... 57 Figure 7 – 100 PIN QFP PACKAGE............................................................................................................................ 58 SMSC DS – USB97C201 FIGURES Page 5 PRELIMINARY Rev. 03/25/2002 ...
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... GENERAL DESCRIPTION The USB97C201 is a USB2.0 Mass Storage Class Peripheral Controller intended for use with standard ATA hard drives and standard ATAPI-5 devices. The device consists of a USB 2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded scratchpad and 768 of program SRAM, and an ATA-66 compatible interface. ...
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... IDE_DRQ IDE_SA1 USBD+ RTERM MD0 MD4 MA0 MA4 MA8 MA12 nMRD GPIO0 GPIO4/nWE XTAL1/CLKIN TST_OUT/DBGOUT POWER, GROUNDS, and NO CONNECTS (23 Pins) SMSC DS – USB97C201 DISK DRIVE INTERFACE (27 Pins) IDE_D1 IDE_D2 IDE_D5 IDE_D6 IDE_D9 IDE_D10 IDE_D13 IDE_D14 IDE_nIOW IDE_IRQ IDE_nCS0 IDE_nCS1 IDE_SA2 IORDY ...
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... USB- FS- RTERM VSSA XTAL1/CLKIN XTAL2 VSSP LOOPFLTR VDDP N.C. N.C. MD7 MD6 MD5 MD4 GND MD3 MD2 MD1 MD0 nRESET 1 SMSC DS – USB97C201 USB97C201 Page 8 PRELIMINARY 51 IDE_D3 IDE_D13 IDE_D2 GND IDE_D14 IDE_D1 IDE_D15 IDE_D0 VDDIO IDE_DRQ IDE_nIOW IDE_nIOR IORDY GND IDE_DACK IDE_IRQ IDE_SA1 ...
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... Address Granted SRAM access during Phase 0 SIE ( Serial Interface Engine ) USB 2.0 PHY ( Transceiver ) OPTIONAL External PHY CLOCKOUT SMSC DS – USB97C201 512 Bytes EP2 TX/RX Buffer B 512 Bytes EP2 TX/RX Buffer A Address 64 Bytes EP1RX 64 Bytes EP1TX 64 Bytes EP0RX 64 Bytes EP0TX 32 Bit 60MHz Latch phase 0 ...
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... IDE_nCS0 Select 0 IDE Chip IDE_nCS1 Select 1 0 IDE Data IDE_D[0:12] IO Ready IORDY SMSC DS – USB97C201 DISK DRIVE INTERFACE IS This pin is the active high DMA request from the ATA/ATAPI interface. O20 This pin is the active low read signal for the interface. O20 This pin is the register select address bit 1 signal for the ATA/ATAPI interface ...
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... Memory Read nMRD Strobe IO Read nIOR Strobe IO Write nIOW Strobe SMSC DS – USB97C201 USB INTERFACE IO-U These pins connect to the USB bus data signals. This pin provides the ability to supplement the internal filtering of the transceiver with an external network, if required. A 9.09 Kohm precision resistor is attached from ground to this pin to set the transceiver’ ...
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... VDD VDDIO VDDP VSSP VDDA VSSA GND NC SMSC DS – USB97C201 MISC ICLKx 12Mhz Crystal or external clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 12Mhz clock when a crystal is not used. OCLKx 12Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN ...
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... BUFFER TYPE DESCRIPTIONS Table 1 - USB97C201 Buffer Type Descriptions BUFFER IO8 O12 IO20 OD12 O20 ICLKx OCLKx I/O-U SMSC DS – USB97C201 DESCRIPTION I Input IS Input with Schmitt trigger Input/Output with 8 mA drive O8 Output with 8mA drive Output with 12mA drive Input/output with 20mA drive Open drain… ...
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... UTIL_CFG register for more information) 0x0000-0x03FF Fixed Memory 8051 MCU External Code Address 0xFFFF 0x0700 0x0400 0x0000 FIGURE 1 - MCU TO EXTERNAL CODE SPACE MAP SMSC DS – USB97C201 Table 2 - MCU Code Memory Map CODE SPACE Space Internal 768 Byte SRAM or External Memory Page 14 PRELIMINARY ACCESS ...
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... MOV instructions. In addition to the normal 8051 SFRs, there are also numerous Runtime Registers in this SFR space. These Runtime Registers are external to the 8051, but internal to the USB97C201. SMSC DS – USB97C201 Table 3 - MCU XData Memory Map ...
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... GPIO_IN C0 GPIO_IRQ 9C GPIO_MSK 9D UTIL_CONFIG 9F SRAM_DATA A1 SRAM_ADD1 A2 SRAM_ADD2 A5 CLOCK_SEL A0 WU_SRC_1 A6 WU_MSK_1 SMSC DS – USB97C201 Table 4 - MCU Block Register Summary R/W DESCRIPTION RUNTIME REGISTERS R/W INT0 Source Register R/W INT0 Mask Register R/W INT1 Source Register R/W INT1 Mask Register R Device Revision Register R Device ID Register UTILITY REGISTERS R/W GPIO Direction Register ...
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... ATA_DMA DF IDE_TIM E1 ATA_CNT0 E2 ATA_CNT1 E3 ATA_CNT2 E4 ATA_CNT3 E5 ATA_SRCA E6 ATA_SRCB SMSC DS – USB97C201 SIE & BUFFER CONTROL REGISTERS R/W USB Address Register R/W SIE Configuration Register R/W USB Bus Status Register R/W USB Bus Status Mask Register R SIE Status Register R/W USB Configuration Number Register R/W SIE Status Mask Register ...
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... Note: the strobe width will vary with the actual clock divider used for the processor. For example if, 16 Mhz is used, an MD[2:0] value of 111 will result clock strobe or 1866ns. SMSC DS – USB97C201 BIT5 BIT4 BIT3 BIT2 ...
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... The bits in this register (except bit 7) are set to their POR values by writing a ‘1’ to the corresponding bit. If not masked by the corresponding bit in the IMR0 mask register, a “1” on any of these bits will generate a “1” on the 8051 core’s external INT0 input. SMSC DS – USB97C201 Table 6 - Interrupt 0 Source Register INTERRUPT 0 SOURCE REGISTER ...
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... Note 1: The bits (except for bit 5)in this register are cleared by writing a ‘1’ to the corresponding bit. If not masked by the corresponding bit in the IMR1 mask register, a “1” on any of these bits will generate a “1” on the 8051 core’s external INT1 input. SMSC DS – USB97C201 Table 7 - Interrupt 0 Mask INTERRUPT 0 MASK REGISTER ...
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... Note 1: The mask bits do not prevent the status in the ISR_1 register from being set, only from generating an interrupt. DEV_REV (0x95- RESET=0xXX) BIT [7:0] XXh DEV_ID (0x96- RESET=0x12) BIT [7:0] 12h SMSC DS – USB97C201 Table 9 - Interrupt 1 Mask INTERRUPT 1 MASK REGISTER R/W DESCRIPTION R/W Zero Length Packet Interrupt Mask 0 = Enable Interrupt 1 = Mask Interrupt R/W Reserved. This bit should never be written to a “0”. R/W ...
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... Utility Registers (0x97- RESET=0x00) BIT GPIO4/nWE 3 GPIO3/T1 2 GPIO2/T0 1 GPIO1/TXD 0 GPIO0/RXD SMSC DS – USB97C201 Table 12 - GPIO Direction Register GPIO_DIR GPIO DIRECTION REGISTER NAME R/W DESCRIPTION GPIO7 R/W GPIO7 Direction Out GPIO6 R/W GPIO6 Direction Out GPIO5 R/W GPIO5 Direction Out R/W GPIO4 Direction ...
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... GPIO0 data out RXD "Uart P3.0" Mux Enable GPIO1 data out TXD "Uart P3.1" Mux Enable GPIO4 data out IDE_nIOW Mux Enable SMSC DS – USB97C201 GPIO out data GPIO in data Edge Detector GPIO2 data out GPIO2 DIR GPIO2 data in 0 TBD ...
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... Note 1: Writing a “1” (one bit clears the bit and enables the detection of the next level transition. If not masked by the corresponding bit in the GPIO_MSK register, “1” in any bit in this register will force a “1” on the 8051 core’s external INT4 interrupt input. SMSC DS – USB97C201 Table 13 - GPIO Output Register GPIO DATA OUTPUT ...
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... GPIO5_MSK 4 GPIO4_MSK 3 GPIO3_MSK 2 GPIO2_MSK 1 GPIO1_MSK 0 GPIO0_MSK SMSC DS – USB97C201 Table 16 – GPIO Interrupt Mask Register GPIO INTERRUPT MASK REGISTER R/W DESCRIPTION R Prevents a high in the corresponding bit in the GPIO_IRQ register from generating an interrupt on the INT4 input to the 8051. R Prevents a high in the corresponding bit in the GPIO_IRQ register from generating an interrupt on the INT4 input to the 8051 ...
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... BIT NAME [7:0] SRAM_DATA SRAM_ADD1 (A1 RESET=0x00) BIT NAME [7:0] SRAM_ADD SMSC DS – USB97C201 Table 17 - Utility Configuration Register UTILITY CONFIGURATION REGISTER R/W DESCRIPTION R The 768 byte SRAM is located at 0x0400- 0x06FF in the Code Space, instead of external Memory The 768 byte SRAM is located at 0x0400- 0x06FF in the XDATA space. ...
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... Note 3: Clock switching can be done on the fly as long as both clocks are running. When switching, it takes a total of six clocks (3 clocks of the original clock plus 3 clocks of the switching clock) to guarantee the switching. Note 4: Time TBD is required from ROSC_EN=1 to MCUCLK_SRC=0. SMSC DS – USB97C201 Table 20 – SRAM Address Register 2 SRAM ADDRESS REGISTER 2 ...
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... Resume 0 EXT_INT Note 1: Interrupt events enabled by these bits are Ored and routed to the INT2 external interrupt input of the 8051 core. SMSC DS – USB97C201 Table 22 - Wakeup Source 1 Register (INT2) WAKEUP SOURCE 1 DESCRIPTION Reserved This bit is set when the SIE detects simultaneous logic lows on D+ and D- (Single-Ended 0) for full speed bit times low speed bit times (or 2.5< ...
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... RESUME interrupts in USB_STAT and WU_SRC_1 registers This bit is cleared by the 8051 during wake-up operations (RESUME or Remote RESUME) to re-power the PHY and enable its clocks. Note: In order for the USB97C201 to generate a remote wake-up using bit 1 of this register, this bit MUST be cleared (0). Page 29 PRELIMINARY DESCRIPTION ...
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... Host is high speed capable. This bit is set if high speed signaling is received from the host. R Indicates that RESUME signaling has been detected. This is only valid if the USB97C201 is in the SUSPEND state via bit 0 of the SIE_CONF register. R Indicates that a USB Reset has been detected. ...
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... SET_REMWU 0 CLR_REMWU Note: The mask bits do not prevent the status in the SIE_STAT register from being set, only from driving the INT3 line of the 8051 core high. SMSC DS – USB97C201 Table 28 – SIE Status Register SIE STATUS REGISTER R/W DESCRIPTION R/W Set to “1” SET_FEATURE_ENDPOINT_HALT command is received on any endpoint by the SIE ...
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... SMSC DS – USB97C201 USB CONFIGURATION NUMBER REGISTER R/W DESCRIPTION R Always returns a “0”. R Reflects the current USB97C201 system as set by the host. ENDPOINT 0 RECEIVE CONTROL REGISTER R/W DESCRIPTION R This bit always reads “0”. R This bit reflects the data toggle state of the last received data token. R/W When set to a “ ...
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... DIR 6 RAMWR_ TOGVALID 5 RAMWR_ TOGGLE SMSC DS – USB97C201 ENDPOINT 1 RECEIVE CONTROL REGISTER R/W DESCRIPTION RESET clears this bit. Writing a “0” to this bit has no effect. R This bit always reads “0”. R/W EP1 Receive is enabled in the SIE if this bit is set to a “1”, otherwise disabled ...
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... COUNT Note: This register is updated at the end of a transfer and is actually the least significant bits of the ending address in the SRAM buffer. SMSC DS – USB97C201 ENDPOINT 2 CONTROL REGISTER R/W DESCRIPTION W Writing a “0” to this bit will begin the output of the 512 byte ...
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... RAMWRBC_A2 (0xCF- RESET=0x00) BIT NAME [7:0] COUNT[7:0] Table 42 – RAM Buffer Write Byte Count Register B1 RAMWRBC_B1 (0xD1 - RESET=0x00) SMSC DS – USB97C201 ENDPOINT 0 TRANSMIT BYTE COUNT REGISTER R/W DESCRIPTION R This bit always reads “0”. R Indicates that 64 Bytes are to be transmitted. R/W Indicates the byte count of the packet to be sent on EP0 and stored in SRAM beginning at address 0x0040 ...
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... COUNT[7:0] NAK (0xD7 - RESET=0x00) BIT NAME 7 NYET2RX 6 NYET0RX 5 NAK2TX SMSC DS – USB97C201 R/W DESCRIPTION R This bit always reads “0” Indicates that 512 bytes were transferred R Bit 8 of the byte count for the data transferred. RAM BUFFER WRITE BYTE COUNT REGISTER B2 R/W ...
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... Reserved 4 STALL 3 DTOG 2 RXERR 1 Reserved 0 CRC SMSC DS – USB97C201 NAK REGISTER R/W DESCRIPTION indicates that an NAK has been sent to the host on Endpoint 2 in response to an OUT token indicates that an NAK has been sent to the host on Endpoint 1 in response token indicates that an NAK has been sent to the host on Endpoint 1 in response to an OUT token ...
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... RESET=0x00) BIT NAME [7:0] D[15:8] ATA_CNT2 (0xE3 - RESET=0x00) BIT NAME [7:0] D[23:16] SMSC DS – USB97C201 USB ERROR REGISTER R/W DESCRIPTION has been received on an endpoint. Table 51 – MSB ATA Data Register MSB ATA CONTROL/STATUS DATA REGISTER R/W DESCRIPTION R/W During 8051 writes to XDATA 0x31F0 (the ATA Drives Control/Status register), data in this register represents the MS byte of the 16 bit operation to this address ...
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... ATA block are unchanged. The firmware may determine which buffer was being used by the ATA at the time of the error by reading either bit 4 or bit 5 of the EP2_CTL register and determine how much of the transfer was completed by reading the ATA_CNx registers. SMSC DS – USB97C201 Table 56 – ATA Transfer Count Register 3 ATA TRANSFER COUNT REGISTER 3 ...
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... RESET=0x00) BIT NAME [7:6] ISP[1:0] [5:4] RT[0:1] 3 DTE SMSC DS – USB97C201 Table 58 –ATA Ultra DMA Timing Register ATA ULTRA DMA TIMING REGISTER R/W R These bits always reads “0”. R/W Drive Timing. These bit settings the Ultra DMA mode that the ATA interface operates when Ultra DMA operation is enabled. ...
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... MWDMA MWDMA MWDMA SMSC DS – USB97C201 IDE TIMING REGISTER R/W DESCRIPTION R/W Prefetch and Posting Enable. 1:Prefetch and posting to the IDE data port is enabled for the drive. 0: Prefetch and posting is disabled for the drive . R/W IORDY Sample Point Enable. 1: All accesses to the ATA I/O address range sample IORDY. ...
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... NYET, STALL, ACK and NACK depending on the endpoint buffer status. During the power down state, the SIE clock is stopped. The SIE can asynchronously detect a USB Reset and/or USB Resume condition and wakeup the 8051. 6.2.1 AUTONOMOUS USB PROTOCOL SMSC DS – USB97C201 ATA SLEW RATE CONTROL A REGISTER R/W DESCRIPTION R/W These two bits are control inputs of the ATA pad for data bits [15:12] ...
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... The maximum packet length of an endpoint is fixed and 64 bytes for EP0 and EP1, and is 512 bytes for EP2 in HS mode and 64 bytes in FS mode. For IN transactions, the USB97C201 will send the bytes in the buffer to the host. For all OUT packets, the number of bytes received in the packet is indicated to the 8051 through the BYTE COUNT Register of the respective endpoint ...
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... This is detected by the SIE when the idle condition on the USB bus occurs for a duration of more than 3ms. Upon detection of this condition via the SUSPEND bit of ISR_1, the 8051 will place the USB97C201 into a low power mode via the USB_SUSPEND bit and enter into a power down state. ...
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... IDE CONFIGURATIONS The USB97C201 supports only a single primary drive on the IDE interface. 6.3.2 PIO IDE OPERATIONS The IDE controller includes both compatible and fast timing modes. The fast timing mode only applies to the IDE data ports ...
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... STOP, STROBE and DMARDY. Table 63 shows the mapping of the redefined Ultra ATA/66 signals onto the standard IDE controller pins. STOP: STOP is always driven by the the USB97C201 and is used to request that a transfer be stopped acknowledgment to stop a request from IDE device. The IDE_nIOW signal is redefined as STOP for both read and write transfers ...
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... STROBE. The receiver can pause the burst stream by negating the nDMARDY and resumes the transfers by asserting nDMARDY. The USB97C201 may pause a burst transaction in order to toggle internal data buffer prevent a buffer over or under flow condition, resuming once the condition has cleared. 1) Termination Phase: Either the source or the receiver can terminate a burst transfer ...
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... Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/66 transfers. The CRC value is calculated for all data by both the USB97C201 and the IDE device over the duration of the DMA burst transfer segment. This segment is defined as all data transferred with a valid STROBE edge from DACK assertion to nDACK deassertion ...
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... The SRAM access, read or write, occurs in four sequential phases, Ø0-3. These periods are 16.666ns long (60Mhz) and are non-overlapping. Data to/from the SRAM are buffered by local DWORD latches close to the SRAM to minimize high-speed bussing. The rest of the USB97C201 subsystems access these latches during the phases when they are NOT being used to transfer data to/from the SRAM. ...
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... On subsequent Ø0 slices, the SIE will read (for IN tokens) or write (for OUT tokens) the appropriate SRAM buffer according to which EP is being accessed, if any, while the USB97C201 transfers the A buffer to the ATA interface during Ø1. When an OUT packet on EP0 is received, the data in the SRAM will be transferred to the SIE on subsequent Ø ...
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... RAMWR_TOGGLE according to the state change of the RAMWR_B and RAMWR_A bits, as shown in Table 65 . These bits are normally set by the USB97C201 upon completion of loading the SRAM buffer and are normally cleared by the firmware (except when Auto Transfer operation is enabled, see Section 6.9.3). Note that when both buffers are “ ...
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... EP2 and the ATA DMA interface. Automatic transfer of byte counts between the RAMWRBC_A/B and RAMRDBC_A/B registers is also implemented. This is illustrated in Figure 5. Note : If the count in RAMWRBC_A/B is zero, no transfer will occur. This is likely to happen on transfers from the SIE to the ATA at the very end of the transfer. SMSC DS – USB97C201 POR RAMRD_A=1 RAMRD_B=1 ...
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... AUT0_TRANS->1 CLR RAMWR_B RAMWR_TOGGLE =1 & CLR RAMWR_B FIGURE 5 - AUTOMATIC DATA TRANSFER OPERATION The trapezoidal shapes represent actions taken by the state machine. SMSC DS – USB97C201 RAMWR_A=0 RAMWR_B=0 RAMRD_A=1 RAMRD_B=1 XFER COUNT No RAMWRBC_A1/2 -> RAMWR_A=1 Yes RAMRDBC_A1/2; & count<>0 ? RAMRD_TOGGLE=0; No RAMWR_B=1 RAMRD_A Yes & count<>0 ? ...
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... ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O8 Type Buffer Low Output Level High Output Level Output Leakage SMSC DS – USB97C201 = 0°C - 70° +3.3 V ± 10 DDIO, DDA SYMBOL MIN TYP V ...
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... Supply Current Standby Note 1: Output leakage is measured with the current pins in high impedance. Note 2: See Appendix A for USB DC electrical characteristics. CAPACITANCE T = 25° 1MHz PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SMSC DS – USB97C201 SYMBOL MIN TYP 2 ...
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... AC SPECIFICATIONS 8.1 ATA/ATAPI The USB97C201 conforms to all timing diagrams and specifications for ATAPI-5 as set forth in the T13/1321D Revision 3 NCITS specification. Please refer to this specification for more information. 8.2 USB2.0 Timing The USB97C201 conforms to all timing diagrams and specifications for USB peripheral silicon building blocks as set forth in the USB-IF USB 2.0 specification. Please refer to this specification for more information. SMSC DS – ...
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... Note 2: Minimum space between protrusion and an adjacent lead is .007 mm. Note 3: Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC DS – USB97C201 FIGURE 6 - 100 PIN TQFP PACKAGE MAX ~ 1 ...
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... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4 Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. SMSC DS – USB97C201 FIGURE 7 – 100 PIN QFP PACKAGE MAX ~ 3.4 ~ ...
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... MCU Memory Map: Code Space 27 Table 21 - MCU Clock Source Select 29 Table 25 – SIE Configuration Register 54 7.0 DC PARAMETERS SMSC DS – USB97C201 CORRECTION Changes on the following (see italicized text): RBIAS, FS-, FS+ Description change (see italicized text) Changes on the following (see italicized text): CLKVALID ...