USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 26

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Note 1: GPIO0, when used as an output, will automatically toggle with 1second period and 50% duty cycle if
SMSC DS – USB97C201
GPIO0_TOG is high.
BIT
7
6
5
4
3
2
1
0
[7:0]
[7:0]
BIT
BIT
(9D RESET=0x00)
GPIO0_TOG
GPIO4/nWE
GPIO0/RXD
GPIO1/TXD
UTIL_CONFIG
SRAMSW
GPIO3/T1
GPIO2/T0
Reserved
NAME
(0x9F- RESET=0x00)
(A1 RESET=0x00)
SRAM_DATA
SRAM_ADD
SRAM_DATA
SRAM_ADD1
NAME
NAME
[7:0]
[7:0]
Table 17 - Utility Configuration Register
Table 19 – SRAM Address Register 1
Table 18 – SRAM Data Port Register
PRELIMINARY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = The 768 byte SRAM is located at 0x0400-
0x06FF in the Code Space, instead of
external Memory.
0 = The 768 byte SRAM is located at 0x0400-
0x06FF in the XDATA space.
Reserved. This bit should never be written to
a “1”.
1 = GPIO0 Output Auto Toggle enabled.
0 = Disabled, normal operation occurs.
GPIO4/SOF Output Select Mux
0 = GPIO4
1 = The IDE_nIOW signal is output.
P3.5 Timer 1 input trigger source
0 = GPIO3
1 = TBD
P3.4 Timer 0 input trigger source
0 = GPIO2
1 = TBD
GPIO1/TXD Output Select Mux
0 = GPIO1
1 = P3.1
P3.0 RXD/GPIO0 Input Select Mux
0 = RXD<=GPIO0
1 = RXD<='0'
Page 26
UTILITY CONFIGURATION REGISTER
Data to be read or written
from/to the buffer SRAM. The
address
determined
SRAM_ADD1/2 registers. Data
to be written will be done so
upon write of this register.
While reads of the register
always reflects the data at the
memory location.
SRAM ADDRESS REGISTER 1
This register contains lower bits
of the address in the buffer
RAM that the SRAM_DATA
register reads or writes.
SRAM DATA PORT
DESCRIPTION
DESCRIPTION
DESCRIPTION
REGISTER
of
the
by
data
the
is
Rev. 03/25/2002