USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 50

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

2.
Phase 0 (Ø0) will refer the 60MHz sub-period that the SIE has access to the SRAM, while Ø1 will be that for the ATA
interface and Ø2 will be for the 8051 (Ø3 is idle and reserved).
During one of the Ø0 periods, the SIE finishes loading the last of the packet data into the B buffer. RAMWR_B
interrupt bit is set notifying firmware of completion of packet. Assuming that the RAMWR_A=0 (the data in the A
SRAM buffer has been previously transferred), the RAMWR_TOGGLE bit is written to a “0” by the firmware, which
clears the RAMWRBC_A1/2 registers and directs the next data received from EP2 to the A buffer space in SRAM.
Firmware reads RAMWRBC_B1/2 to determine packet size, loads value into RAMRDBC_B1/2 register. The
RAMRD_TOGGLE bit of EP2_CTL is written by the firmware with a “1” which will begin the transfer of the B buffer to
ATA interface on the next Ø1 period.
On subsequent slices, the next DWORD of the incoming data packet from the host is loaded into the A buffer space
on Ø0 from the SIE, auto-incrementing the RAMWRBC_A1/2 register values. On Ø1 slices, the data from the B
buffer space is output to the ATA interface (appropriately flow controlled by that interface), and incrementing a
counter which is compared to the RAMRDBC_B1/2 registers to determine if the transfer is completed. During this
time, the SIE receives an IN on EP0. During the next Ø0 periods, and until the final transmission of the packet data
to the SIE is completed, data is read from the SRAM into the SIE for EP0 in response to INs. The writing of the A
buffer by the SIE on Ø0 periods will then resume with the reception of OUTs on EP2.
Assuming the incoming data completes loading into the A buffer space, before the B buffer is transferred to the ATA
interface, the RAMWR_A interrupt will be generated before the RAMRD_B interrupt. The firmware will then wait until
the RAMRD_B interrupt occurs, loads the RAMRDBC_A1/2 register with the count from the RAMWRBC _ A1/2
registers, flips the buffers (ie RAMRD_TOGGLE=0, RAMWR_TOGGLE=1), and clears the RAMWR_B bit (allowing
the reuse of the B buffer area).
On subsequent Ø0 slices, the SIE will read (for IN tokens) or write (for OUT tokens) the appropriate SRAM buffer
according to which EP is being accessed, if any, while the USB97C201 transfers the A buffer to the ATA interface
during Ø1. When an OUT packet on EP0 is received, the data in the SRAM will be transferred to the SIE on
subsequent Ø0 slices, DWORD at a time until completed.
6.9 EP2 Automatic Buffer Operations
Automatic operation of the interleaved SRAM buffers exists in two degrees: Automatic toggling of input buffers and
automatic transfer of input and output buffer data to/from the SIE and ATA interface. These features may be disabled
via bits in the ATA_CTL register.
6.9.1
If the AUTO_TOG bit of the ATA_CTL register is set to a “1”, then receive auto-toggling between the A and B buffers
for writes to the SRAM is enabled. Figure 3 illustrates the auto-toggle of the receive buffers.
SMSC DS – USB97C201
Endpoint 2 will be receiving more data (short packet, ie end of file segment) followed by a OUT packet from the
host on the control endpoint (EP0) requesting data. Data has already been placed in the SRAM EP0 TX Buffer,
its length loaded into the EP0TX_BC register, and the TX bit of the EP0TX_CTL register written to a “1”.
RECEIVE AUTO-TOGGLE
PRELIMINARY
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Rev. 03/25/2002