USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 52

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

Transmit buffer operations are always initiated by writing the RAMRD_TOGGLE bit in the EP2 Control register.
Output flow control to the device receiving data from the SRAM buffer is active once data in both buffers has been
transferred. If the destination is the SIE, then it will NYET or NAK further INs. If it is the ATA interface, nDAK will not
be asserted in response to DRQ data will not be clocked out.
6.9.3
If the AUTO_TRANS bit is set in the ATA_CTL register, then automatic manipulation of the RAMWR_TOGGLE,
RAMRD_TOGGLE, RAMWR_B, and RAMWR_A bits is executed by a state machine to allow continuous streaming
of the data between EP2 and the ATA DMA interface. Automatic transfer of byte counts between the
RAMWRBC_A/B and RAMRDBC_A/B registers is also implemented. This is illustrated in Figure 5.
Note : If the count in RAMWRBC_A/B is zero, no transfer will occur. This is likely to happen on transfers from the SIE
to the ATA at the very end of the transfer.
SMSC DS – USB97C201
AUTOMATIC TRANSFER OPERATION
RAMRD_B=0
TOGGLE=
RAMRD_
No
0?
Yes
Yes
FIGURE 4 - TRANSMIT BUFFER OPERATION
No
Output A Buffer
RAMRD_B=0?
RAMRD_A=0;
RAMRD_A=1
SRAM Data
Completed?
RAMRD_
TOGGLE
Written?
Output
Begin
Yes
PRELIMINARY
No
Yes
No
FLOW CONTROL
FLOW CONTROL
RAMRD_A=1
RAMRD_B=1
INACTIVE
TOGGLE=
RAMRD_
TOGGLE
RAMRD_
OUTPUT
OUTPUT
Yes
ACTIVE
Written?
POR
Page 52
Yes
No
0?
Yes
No
No
Output B Buffer
RAMRD_A=0?
RAMRD_B=0;
RAMRD_B=1
SRAM Data
Completed?
RAMRD_
TOGGLE
Written?
Output
Begin
Yes
No
Yes
RAMRD_A=0
TOGGLE=
RAMRD_
No
1?
Yes
Rev. 03/25/2002