USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 45

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

The most significant byte of transfer to/from this Data Port is available to the 8051 via the register located in SFR
space at 0xDB. Writes to 0x31F0 in the XDATA space by the 8051 would write both the contents of this register and
the data in the MOVEX instruction as a 16 bit DWORD to the ATA Data Port. Similarly, reads by the 8051 of 0x31F0
will return the actual drive data for reading by the 8051 at 0xDB and 0xDC.
6.3.1
The USB97C201 supports only a single primary drive on the IDE interface.
6.3.2
The IDE controller includes both compatible and fast timing modes. The fast timing mode only applies to the IDE
data ports. All other transactions to the IDE registers are run in single transaction mode with compatible timings.
The IDE_TIM register permits different timing modes, from Multi-word DMA ATA Mode 0 to ATA Mode 2, to be
programmed for the drive. These modes range from 3MB/sec to 16MB/sec in terms of data transfer rate. The Ultra
ATA/66 synchronous DMA timing modes can also be applied to each drive by programming the ATA_CTL and
ATA_DMA registers. When a drive is enabled in Ultra DMA mode operation, the DMA transfers are executed with the
Ultra ATA timings. The PIO data transfers are still executed using compatible timings or fast timings when enabled.
PIO accesses are not directly made to the drive from the 8051 via its XDATA address space, but are timed by the
ATA controller to meet required drive timing. A read access is accomplished by first reading the XDATA address
location, ignoring the returned data, and then waiting for the PIO_COMPLETE bit to be set in the ATA_CTL register.
The actual data retrieved from the drive can then be read at LSB and MSB( if a 16 bit access to 31F0) ATA Data
registers in SFR space. Writes to the drive are done normally, directly to the XDATA address desired( the MSB ATA
Data register must be loaded first for the 16 bit writes to 31F0), but a subsequent write (or read) cannot be initiated
until the PIO_COMPLETE bit is set. This bit is reflected in the ISR_1 register to allow an interrupt to be generated, if
desired.
Startup Latency: If the IDE_SA[2:0] and IDE_nCS[1:0] lines are not set up, startup latency is incurred when a cycle
that accesses the IDE data port is decoded. Startup latency provides the setup time for assertion of IDE_SA[2:0] and
IDE_nCS[1:0] lines prior to assertion of the read and write strobes (IDE_nIOR and IDE_nIOW).
Cycle Latency: Cycle latency consists of the I/O command strobe assertion length and recovery time. Recovery time
is needed so that back-to-back transactions, which does not incur startup and shutdown latency, may occur on the
IDE interface without violating minimum cycle periods for the IDE interface. The command strobe assertion width
(IORDY Sample Point: ISP) for the fast timing mode is programmable in the ISP field of the IDE_TIM Register. The
recovery time (RCT) is programmable in the RCT field of the IDE_TIM Register.
If the IORDY is asserted when the IORDY sample point is reached, no wait states are added to the command strobe
assertion length. If IORDY is negated when the sample point is reached, additional wait states are added.
IORDY Masking: The IORDY signal can be ignored and assumed asserted at the first IORDY Sample Point (ISP)
through the IDE_TIM register.
Shutdown Latency: Shutdown latency is incurred after the IDE data transactions (either a non-empty write post
buffer to the IDE drive or an outstanding read prefetch cycles from the IDE drive) have completed and before other
IDE transactions can proceed. The latency provides hold time on the IDE_SA[2:0] and IDE_nCS[1:0] lines with
respect to the read and write strobes (IDE_nIOR and IDE_nIOW). Shutdown latency is set to 67ns in duration.
Table 62 shows the IDE cycle timings for various IDE transaction types.
6.3.3
The IDE Controller can be programmed via the IDE_TIM registers to allow data to be posted to and prefetched from
the IDE data ports. Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency
to the IDE data ports and allows them to be performed back to back for the highest possible PIO data transfer rates.
SMSC DS – USB97C201
IDE CONFIGURATIONS
PIO IDE OPERATIONS
PIO IDE DATA PREFETCHING AND POSTING
Non-Data Port Compatible
Data Port Compatible
Fast Timing Mode (for Data Port
Accessing)
IDE TRANSACTION TYPE
Table 62 – IDE Transaction Timing
PRELIMINARY
STARTUP
LATENCY
133ns
100ns
67ns
Page 45
267-167ns
367ns
200ns
ISP
33-133ns
733ns
467ns
RCT
SHUTDOWN
LATENCY
67ns
67ns
67ns
Rev. 03/25/2002