USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 42

• Manufacturer Part Number: USB97C201-MN
• Description: USB 2.0 ATA/ ATAPI Controller
• Manufacturer: SMSC [SMSC Corporation]

6.2 SIE Block
The SIE is a USB low-level protocol interpreter. The SIE controls the USB bus protocol, packet generation /
extraction, PID / Device ID parsing, and CRC coding / decodingwith autonomous error handling.
Parallel-to-serial / serial-to-parallel conversion, bit stuffing, and NRZI coding / decoding are handled in the PHY
block.
It is capable of operating either in USB 1.1 or 2.0 compliant modes. Unlike the normal 97Cxxx series SIEs, it has
more autonomous protocol handling functions like stall condition clearing on setup packets, suspend / resume / reset
conditions, and remote wakeup. It also autonomously handles the error conditions such as retry for CRC errors, Data
toggle errors, and generation of NYET, STALL, ACK and NACK depending on the endpoint buffer status.
During the power down state, the SIE clock is stopped. The SIE can asynchronously detect a USB Reset and/or
USB Resume condition and wakeup the 8051.
6.2.1
SMSC DS – USB97C201
[7:6]
[5:4]
[3:2]
[1:0]
[7:2]
[1:0]
BIT
BIT
AUTONOMOUS USB PROTOCOL
(0xE5 - RESET=0x00)
(0xE6 - RESET=0x00)
Reserved
SLEW3
SLEW2
SLEW1
SLEW0
SLEW4
NAME
NAME
ATA_SRCA
ATA_SRCB
Table 60 –ATA Slew Rate Control A Register
Table 61 –ATA Slew Rate Control B Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
PRELIMINARY
These two bits are control inputs of the ATA pad for data
bits [15:12]. The bits can be used to vary the slew rate of
IDE_D[15:12] from minimum to maximum rate specified by
the ATA66 specification. The value 11b sets the slew rate
to be the maximum and the value of 00b sets the slew rate
to be the minimum.
These two bits are control inputs of the ATA pad for data
bits [11:8]. The bits can be used to vary the slew rate of
IDE_D[11:8] from minimum to maximum rate specified by
the ATA66 specification. The value 11b sets the slew rate
to be the maximum and the value of 00b sets the slew rate
to be the minimum.
These two bits are control inputs of the ATA pad for data
bits [7:4]. The bits can be used to vary the slew rate of
IDE_D[7:4] from minimum to maximum rate specified by the
ATA66 specification. The value 11b sets the slew rate to be
the maximum and the value of 00b sets the slew rate to be
the minimum.
These two bits are control inputs of the ATA pad for data
bits [3:0]. The bits can be used to vary the slew rate of
IDE_D[3:0] from minimum to maximum rate specified by the
ATA66 specification. The value 11b sets the slew rate to be
the maximum and the value of 00b sets the slew rate to be
the minimum.
Always returns “0” on reads
These two bits are control inputs of the ATA pad for
STROBE signaling during Ultra ATA writes to disk. The bits
can be used to vary the slew rate of STROBE from
minimum to maximum rate specified by the ATA66
specification. The value 11b sets the slew rate to be the
maximum and the value of 00b sets the slew rate to be the
minimum.
Page 42
ATA SLEW RATE CONTROL A REGISTER
ATA SLEW RATE CONTROL B REGISTER
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002