USB97C201-MN SMSC [SMSC Corporation], USB97C201-MN Datasheet - Page 36

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USB97C201-MN

Manufacturer Part Number
USB97C201-MN
Description
USB 2.0 ATA/ ATAPI Controller
Manufacturer
SMSC [SMSC Corporation]
Datasheet
SMSC DS – USB97C201
[7:2]
[7:2]
[7:2]
BIT
BIT
BIT
BIT
[7:0]
[7:0]
[7:0]
BIT
BIT
BIT
7
6
5
1
0
1
0
1
0
(0xD2 - RESET=0x00)
(0xD3 - RESET=0x00)
(0xD4 - RESET=0x00)
(0xD5 - RESET=0x00)
(0xD6 - RESET=0x00)
(0xD7 - RESET=0x00)
COUNT[7:0]
COUNT[7:0]
COUNT[7:0]
NYET2RX
NYET0RX
Reserved
RAMWRBC_B2
Reserved
Reserved
512Bytes
512Bytes
512Bytes
NAK2TX
COUNT8
RAMRDBC_A1
COUNT8
RAMRDBC_A2
RAMRDBC_B1
COUNT8
RAMRDBC_B2
NAME
NAME
NAME
NAME
NAME
NAME
NAME
NAK
Table 43 – RAM Buffer Write Byte Count Register B2 Register
Table 45 – RAM Buffer Read Byte Count Register A2 Register
Table 47 – RAM Buffer Read Byte Count Register B2 Register
Table 44 – RAM Buffer Read Byte Count Register A1
Table 46 – RAM Buffer Read Byte Count Register B1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
Table 48 – NAK Register (INT5)
PRELIMINARY
This bit always reads “0”.
1 = Indicates that 512 bytes were transferred
Bit 8 of the byte count for the data transferred.
Bits 7 thru 0 the byte count of the data transferred to SRAM.
The packet is stored beginning at address 0x0300.
This bit always reads “0”.
1 = Indicates that 512 bytes are to transferred
Bit 8 of the byte count for the data to be transferred.
Bits 7 thru 0 the byte count of the packet to be transferred
from the SRAM. The packet is stored beginning at address
0x0100
This bit always reads “0”.
1 = Indicates that 512 bytes are to transferred
Bit 8 of the byte count for the data to be transferred.
Bits 7 thru 0 the byte count of the packet to be transferred
from the SRAM. The packet is stored beginning at address
0x0300.
1 = indicates that an NYET has been sent to the host on
Endpoint 2 in response to an OUT token.
1 = indicates that an NYET has been sent to the host on
Endpoint 0 in response to an OUT token.
1 = indicates that an NAK has been sent to the host on
Endpoint 2 in response to an IN token.
RAM BUFFER WRITE BYTE COUNT REGISTER B2
RAM BUFFER READ BYTE COUNT REGISTER A1
RAM BUFFER READ BYTE COUNT REGISTER A2
RAM BUFFER READ BYTE COUNT REGISTER B1
RAM BUFFER READ BYTE COUNT REGISTER B2
Page 36
NAK REGISTER
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
Rev. 03/25/2002

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