HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 100

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Enable Register. Defined interrupt-causing events are
listed in Table 11. When the INTHW output is asserted,
one or more bits are set in the Pending Interrupt Regis-
ter, to identify the interrrupt event(s).
Assertion of the INTMES interrupt after a message is
completed indicates a predetermined message event
occurred that is (1) globally enabled in the Interrupt En-
able Register and (2) specifically enabled for the last
command transacted. The Descriptor Table Control
Word for each command is programmed by the host to
enable events that generate message interrupts. The
type of INTMES event is reflected in the IXEQZ, IWA,
IBR, ILCMD and MERR bits within the Pending Interrupt
Register.
The interrupt architecture maintains information for the
last 16 interrupts in a 32-word ring buffer. The device
automatically handles interrupt-logging overhead. Each
interrupt generates two words of information to help the
host perform interrupt processing. The Interrupt Identifi-
cation Word (IIW) identifies the type(s) of interrupt that
occurred. The Interrupt Address Word (IAW) identifies
the interrupt source (e.g., subaddress Descriptor Block)
using a 16-bit address.
13.2.1. Interrupt Log Address Register
Bits 7:0 in this register indicate the IIW storage address
within the buffer for the next occurring interrupt, 0x0040
to 0x005E. Bits 15:8 indicate the number of interrupts
since the register was last read. For further details, see
the full description of the Interrupt Log Address Register.
13.2.2. Interrupt Address Word (IAW)
Stored in the Interrupt Log Buffer, Interrupt Address
Words (IAW) identify interrupt-causing messages by
storing the descriptor block address for the subaddress
or mode code command that generated each message
interrupt.
13.2.3. Interrupt Identification Word (IIW)
Stored in the Interrupt Log Buffer, Interrupt Identification
Words identify type of interrupt event. Bit assignments
match those used in the Pending Interrupt Register. The
host or subsystem reads the IIW to determine which
type of interrupt occurred. The Interrupt Identification
Word is defined in Table 11.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
100
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IIW - Interrupt Identification
Table 11. Interrupt Identification Word
Interrupt
IXEQZ
IWA
IBR
--------
--------
MERR
--------
ILCMD
SPIFAIL
LBFA
LBFB
TTINT1
TTINT0
RTAPF
EECKF
RAMIF
Word
Origin
Message
Message
Message
--------
--------
Message
--------
Message
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Hardware
Word Descriptor
IAW - Interrupt
Address Word
the Command
Table Address
IAW contains
IAW contains
0x0000