HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 44

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Bit No.
7,6
9
8
5
4
3
2
1
0
Mnemonic
RBPASS
RBFAIL
-----
LBALOG
LBSYNC
LBBUSEL
LBSTART
LBPASS
LBFAIL
R/W Reset Function
R/W
R/W
R/W
R/W
R
R
R
R
R
0
0
0
0
0
0
0
0
0
RAM BIST Pass.
Device logic asserts this bit when the selected RAM test completes without
error. This bit is automatically cleared when RBSTRT bit 10 is set.
RAM BIST Fail.
Device logic asserts this bit when failure occurs while performing the
selected RAM test. This bit is automatically cleared when RBSTRT bit 10
is set. When BIST failure occurs, a clue to the failing RAM address can
be read at register address 0x001E. For speed, the RAM BIST concur-
rently tests 4 quadrants of the RAM address range, in parallel. If test
failure occurs, register address 0x001E contains the RAM address be-
ing tested in the lowest RAM quadrant. Actual failure will occur in any of
these four locations: at RAM address “ADDR” stored in register 0x001E, or
ADDR+0x2000, or ADDR+0x4000 or ADDR+0x6000.
Not Used. These bits cannot be set. A READ will return 0x0000.
Loopback Test Analog.
The device supports either digital or analog loopback testing for either bus
transceiver. When the LBALOG bit is low, digital loopback is selected and
no data is transmitted onto the selected external MIL-STD-1553 bus. When
the LBALOG bit is high, analog loopback is selected and a test word is
transmitted onto and received from the selected external MIL-STD-1553
bus.
Loopback Test Word Sync Select.
When the LBSYNC bit is high, the loopback test word is transmitted with
command sync. When the LBSYNC bit is low, the loopback test word is
transmitted with data sync.
Loopback Test Bus Select.
When this bit is low, loopback testing occurs on Bus A. When this bit is
high, loopback testing occurs on Bus B.
Loopback Test Start.
Writing logic 1 to this bit initiates the loopback test selected by register bits
3, 4 and 5. The LBSTRT bit can only be set if the external TEST pin is al-
ready asserted, and is automatically cleared upon test completion. Register
bits 1,0 indicate pass / fail test result.
Loopback Test Pass.
Device logic asserts this bit when the selected RAM test completes without
error. This bit is automatically cleared when LBSTART bit 2 is set.
Loopback Test Fail.
Device logic asserts this bit when failure occurs while performing the
selected loopback test. Failure is comprised of Manchester encoding error,
parity error, wrong sync type or data mismatch. This bit is automatically
cleared when LBSTART bit 2 is set.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
44