HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 64

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

Bit No. Mnemonic R/W
13
12
11
10
9
IBR
MKBUSY
DBAC
DPB
BCAST
Reset
SR = 0
SR = 0
SR = 0
0
0
0
0
0
Function
Interrupt Broadcast Received.
If the Interrupt Enable Register IBR bit is high, assertion of this bit enables
interrupt generation at each instance of a valid broadcast receive mode code
command. Upon completion of command processing, when IBR interrupts
are enabled, an IBR interrupt is entered in the Pending Interrupt Register, the
INTMES output pin is asserted, and the interrupt is registered in the Inter-
rupt Log. This bit has no function if the BCSTINV bit is high in Configuration
Register 1. In this case, commands to RT address 31 are not recognized as
valid by the device.
Make Busy.
The host asserts the MKBUSY bit to respond with Busy status for commands
to this mode code. This bit is an alternative to globally applying Busy status
for all valid commands, enabled from the 1553 Status Bits Register. See that
register description for additional information. When Busy is asserted, mode
data words received with MC16-MC31 are not stored and the DPB bit does
not toggle after message completion.
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message pro-
cessing. The host may poll this bit to detect mode command activity, instead
of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST
software reset or a read cycle to this memory address.
Data Pointer B.
This status bit is maintained by the device and only applies for mode com-
mands using ping-pong buffer mode. This bit indicates the buffer to be used
for the next occurring mode command. When the DPB bit is logic 0, the next
message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
error-free message completion. The DPB bit is not altered after messages
ending in error, after illegal commands, or after messages when the terminal
responds with Busy status. This bit is reset to logic 0 by MR master reset or
SRST software reset; therefore the first message received after either reset
will use Buffer A. This bit is “don’t care” for indexed single-buffer mode.
Broadcast Received.
Device logic sets this bit when a valid broadcast mode command is received
having T/R bit = 0. This bit has no function if the BCSTINV bit is asserted in
Configuration Register 1. In this case, RT address 31 commands are not rec-
ognized as valid by the HI-6120/21. This bit is reset to logic 0 by MR master
reset or SRST software reset.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
64