HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 104

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

NOTES:
1. After Master Reset, bits 15, 14 and 2 in the BIT Word Register depend on input pin settings. See register descrip-
2. Upon SRST reset, the DBAC, DPB, MKBUSY and BCAST bits are reset for each of the 128 Control Words in the
tion. If the MTSTOFF input pin is low, register bit 3 (BMTF) depends on memory test outcome. The remaining bits
are unconditionally reset. However if auto-initialization is enabled and EEPROM load failure occurs during the
subsequent initialization process, register bit 1 (EELF) will be set.
primary Descriptor Table which starts at address 0x0200. If secondary Descriptor Tables are used (above address
0x0400), the host must perform any necessary table reconfiguration after SRST reset.
0x0400-0x7FFF
0x0020-0x003F
0x0040-0x005F
0x0060-0x00FF
0x0100-0x01FF
0x0200-0x03FF
Hex Address
Prior Bus Shutdown by Mode Cmd MC4 or MC20
Prior Terminal Flag Inhibit by Mode Cmd MC6
Command Processing & ACTIVE Output
Hardware Encoders and Transmitters
Terminal Status (incl ME & BCR bits)
INTMES & INTHW Interrupt Outputs
Hardware Bus Decoders
Temporary Receive Data Buffer, 32 Words
Descriptor Table (Primary), 512 Words
Terminal Function
Secondary Descriptor Tables, if used
READY Output
Illegalization Table, 256 Words
Interrupt Log Buffer, 32 Words
Unallocated RAM, 160 Words
Host-Assigned Data Buffers
RAM Structure
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
104
Contents after MR
negated (high)
overridden
overridden
Reset
Contents after MR
reset
reset
reset
reset
reset
all 0x0000
all 0x0000
all 0x0000
all 0x0000
all 0x0000
all 0x0000
all 0x0000
Reset
after SRST
overridden
overridden
Contents
negated
Reset
(high)
reset
reset
reset
reset
set
after SRST
See Note 2
no change
no change
no change
no change
no change
no change
Contents
Reset