HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 16

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

3. FUNCTIONAL OVERVIEW
The Holt HI-6120 or HI-6121 provides a complete Re-
mote Terminal (RT) interface between a host and a
MIL-STD-1553B dual redundant data bus. It automati-
cally handles all aspects of the MIL-STD-1553 protocol,
namely, encoding/decoding, message formatting, error
checking, message data buffering, protocol checking,
illegalization and default terminal responses. Internal
static RAM is shared by the host and device logic, pro-
viding efficient storage for message data and informa-
tion about messages, updated after each message
transaction. The shared RAM also contains host-initial-
ized tables that define terminal operation.
Two options are offered for host interface. The HI-6120
uses a 16-bit tri-state data bus, ideally suited for memo-
ry-mapped host processor operation. The HI-6121 uses
a 3-wire Serial Peripheral Interface (SPI) with powerful
SPI command set.
Figure 2 shows address mapping for registers and RAM.
Registers occupy the lowest 32 addresses of the 32K
memory address space. Internal registers (or contained
bit fields) are partitioned as read-only or read-write so
the host can exercise configuration control without risk
of misconfiguration caused by accidental writes to de-
vice-maintained registers or bit fields.
Dedicated output pins convey status to the host, and
generate host interrupts for preselected events. Before
processing messages, internal registers and transmit
data buffers in shared RAM must be initialized by the
host to define the desired message responses. Host ini-
tialization can be replaced by optional auto-initialization
using parameters in external EEPROM.
3.1.
3.1.1.
The host-initialized Descriptor Table, residing in shared
RAM, defines terminal response to valid commands.
The table is comprised of 4-word Descriptor Blocks.
Each of 32 subaddresses and 32 mode code values
has two descriptor blocks, one for transmit and one for
receive, for a total of 128 descriptor blocks. The first
word in each descriptor block defines message options
(interrupt selections, data buffer mode, etc.). Except for
Indexed buffer mode (where one word counts messag-
es) the remaining three words point to allocated data
storage in shared RAM. After Master Reset is negated
and before message processing, the host must initialize
descriptor blocks for each utilized subaddress and mode
code. Unused subaddresses and unimplemented mode
Shared RAM Utilization
Descriptor Table
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
16
codes may be illegalized (see below). The Descriptor
Table Base Address Register is initialized with the start-
ing address of the Descriptor Table. Multiple Descriptor
Tables can be used for fast context switching, with the
active table designated by the base address register.
3.1.2.
Optional illegal command detection utilizes an Illegal-
ization Table in the shared RAM. The table can illegal-
ize any logical combination of 11 command word bits
for subaddress, T/R bit and word count (or mode code),
plus broadcast vs non-broadcast status, resulting in a
total of 4,096 possible combinations. The Illegalization
Table Base Address Register is initialized with the ta-
ble’s start address. Terminal response to an illegal com-
mand sets “message error” status and transmits Status
Word only. If illegal command detection is not used (that
is, no “illegal” entries in Illegalization Table), the terminal
responds “in form” to all valid commands.
3.1.3.
After master reset, all locations in shared memory are re-
set to 0000 hex. Ordinary transmit or receive commands
transfer 1 to 32 data words. These are called “subad-
dress commands,” distinguishing them from “mode code
commands,” described in the next paragraph. By ini-
tializing the Descriptor Table, the host allocates space
in shared RAM for storing message data words and
message information words. Data pointers in the table
assign separate data buffer addresses in memory for
each command. Data storage arrangement differs by
choice of data buffer method. Two examples are shown
for each of the four buffer modes in Figures 11-18. After
successfully transacting a message with one or more re-
ceived data words, the RT writes into the assigned data
buffer. While transacting a message with one or more
transmitted data words, the RT reads data for trans-
mission from the assigned data buffer. Before transmit
commands occur, the host should write desired data into
assigned transmit data buffers in shared RAM. Trans-
mit subaddress data buffers can be optionally loaded by
auto-initialization.
3.1.4.
MIL-STD-1553 defines “mode code commands” that are
used for command and control, instead of data transfer.
The various “mode commands” transfer a single data
word, or no data word at all. The user has two choices for
storing mode command data: (1) similar to subaddress
command data, mode command data can be stored in
RAM data buffers assigned by the host-initialized De-
scriptor Table, or (2) When “simplified mode command
processing” is chosen, mode command data is stored
Illegalization Table
Message Data Buffers
Storage for Mode Code Commands