HI-6120 HOLTIC [Holt Integrated Circuits], HI-6120 Datasheet - Page 102

• Manufacturer Part Number: HI-6120
• Description: MIL-STD-1553 Remote Terminal ICs
• Manufacturer: HOLTIC [Holt Integrated Circuits]

ing to RAM address 0x0020. The stored checksum
is tallied as if RAM address 0x0020 equals 0x0000
and five registers are excluded from checksum com-
putation: Operational Status register 0x0002, Pend-
ing Interrupt register 0x0006, Time-Tag register
0x0008 and BIT Word register 0x0014. The stored
value is actually the twos-complement of the 16-bit
memory checksum, (CHECKSUM + 1).
During initialization, byte pairs are sequentially read
from EEPROM, then merged to a 16-bit value that is
both written to device RAM (or register) and added
(running tally) to the twos-complemented checksum
value. When the full 1K or 32K EEPROM range is
tallied, the running checksum tally should equal
zero, indicating error-free checksum tally. After ini-
tialization (at READY assertion), the 16-bit twos-
complement checksum value is copied from EE-
PROM to device RAM address 0x0020. This is part
of the Temporary Receive Data Buffer, which does
not interfere with terminal initialization.
When the device completes auto-initialization, the
READY output pin is asserted to the high state.
If an initialization error occurred, the following events
take place immediately after READY assertion:
1. The INTHW interrupt output pin is asserted.
2. The Operational Status Register 0x0002 is writ-
3. The EELF bit is set in the Built-In Test Word
4. If RAMIF read-back error occurred, the address
The STEX bit in Configuration Register 1 is still zero.
If the STEX bit in the initialization EEPROM is
high, and if the EECKF, RAMIF and RTAPF bits are
reset in the Operational Status Register 0x0002, the
device now sets the STEX bit to start Remote Ter-
minal operation. This means: (1) auto-initialization
was error-free and (2) the RT address in Opera-
tional Status Register bits 15-10 has correct parity.
The register’s terminal address bits reflect input pin
states if the LOCK pin is high, or were overwritten by
values from the initialization EEPROM, if the LOCK
pin is low.
ten to indicate the type of error. The EECKF or
RAMIF bit is set to show checksum failure or
read-back data mismatch between RAM and
EEPROM.
Register 0x0014.
of the first occurring instance is written to regis-
ter address 0x001F. Additional locations beyond
the saved address may have mismatch, but
only the first instance is logged.
HOLT INTEGRATED CIRCUITS
HI-6120, HI-6121
102
A method for programming the EEPROM itself from a
fully configured terminal is explained in a following sec-
tion entitled “Serial EEPROM Programming Utility”. If a
different method is used for writing the serial EEPROM,
the twos-complemented checksum (described earlier)
must be saved in EEPROM locations corresponding to
device RAM address 0x0020.
A compatible serial EEPROM uses a SPI interface for
byte-access read and write operations. Sixteen-bit reg-
ister and RAM values in the HI-612X are stored as upper
and lower bytes in the EEPROM, in “big endian” fashion.
For example, the upper byte for register address 0x0000
is stored at EEPROM address 0x0000 while the lower
byte is stored at EEPROM address 0x0001. A 64K x 8
EEPROM is required to store the entire 32K x 16 ad-
dress range.
Serial EEPROM data mapping follows the device mem-
ory map shown in Figure 2. The single exception: two
EEPROM locations corresponding to device RAM ad-
dress 0x0020 must contain the expected checksum
value. The serial EEPROM used for auto-initialization
should be fully written to cover the HI-6120/21 upper
address limit of 0x7FFF (or 0x03FF, depending on the
state of the EE1K input pin). Ideally the EEPROM image
will reflect a post-MR reset followed by fresh initialization
with nothing written to reset-cleared registers or RAM
as a result of command processing.
If automatic STEX assertion was blocked because
EECKF or RAMIF bits were written high after READY
assertion, the host can write STEX high, overriding
the error condition. If STEX assertion was blocked
because of RT address parity error, the STEX bit
cannot be asserted until the parity error is corrected.
The host may overwrite the Operational Status Reg-
ister RTAP4-0 and RTAP bits to correct the error,
then assert the STEX bit in Configuration Register 1.
If the STEX bit in the initialization EEPROM is
low, the STEX bit in Configuration Register 1 is not
asserted at this time. The device awaits STEX as-
sertion by a host write to Configuration Register 1
before starting Remote Terminal operation. The
STEX bit may be written any time after the READY
output pin goes high.
After any MR master reset, the state of certain input
pins (AUTOEN, LOCK and terminal address pins
RTA4 to RTA0 and RTAP) are latched into Opera-
tional Status Register 0x0002. Because auto-initial-
ization follows master reset, the mirrored pin states
may be overwritten by the values stored in the ini-
tialization EEPROM bytes corresponding to register
address 0x0002, only if the LOCK input pin is low.