K9K1208D0C Samsung semiconductor, K9K1208D0C Datasheet
K9K1208D0C
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K9K1208D0C Summary of contents
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... KM29W8000T -> K9F8008W0M-TCB0 - KM29W8000IT -> K9F8008W0M-TIB0 The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 Bit NAND Flash Memory FEATURES Voltage supply : 2.7V ~ 5.5V Organization - Memory Cell Array : (1M + 32K)bit x 8bit - Data Register : (256 + 8)bit x8bit Automatic Program and Erase(Typical) - ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 PRODUCT INTRODUCTION The K9F8008W0M is an 8.6Mbit(8,650,752 bit) memory organized as 4096 rows by 264 columns. Spare eight columns are located from column address of 256 to 263. A 264-byte data register is connected to memory cell arrays ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F8008W0M-TCB0 Temperature Under Bias K9F8008W0M-TIB0 Storage Temperature Short Circuit Output Current NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 VALID BLOCK Parameter Valid Block Number NOTE : K9F8008W0M 1. The K may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically, an invalid block will contain a single bad bit. The information ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung mini- mizes the additional block failure rate, which ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60H Write Block Address Write D0H Write 70H SR R Erase Error SR Erase ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 System Interface Using CE don’ t -care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 256byte page registers are utilized as seperate buffers for this operation ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLH CLS ALS ALH ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 * Input Data Latch Cycle CLE CE t ALS ALE Sequential Out Cycle after Read ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE CE WE ALE 00h I Column Address R/B t CLS t ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE I 00h Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE 50H I ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00H I R/B M PAGE PROGRAM OPERATION CLE CE WE ALE RE I/O ~ 80H ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 BLOCK ERASE OPERATION CLE CE WE ALE RE 60H I Page(Row) Address R/B Auto Block Erase Setup Command (ERASE ONE BLOCK DOH 19 Busy ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg- ister along with three address cycles. Once the command is latched, ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50H Start Add.(3Cycle) I & Don t Care) Figure 5. Sequential Row Read1 ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 Figure 6. Sequential Row Read2 Operation R/B I 50H Start Add.(3Cycle & Don t Care) PAGE PROGRAM The device is programmed basically on ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 BLOCK ERASE The Erase operation is done on a block(4K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A block address loading initiates the internal erasing process. This ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 READ ID The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of 00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (6EH) respectively. ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or ...
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K9F8008W0M-TCB0, K9F8008W0M-TIB0 PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F #44(40) #1 18.81 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 #23(21) #22(20) Max. 0.80 0.0315 25 FLASH MEMORY Unit ...