K9K1208Q0C Samsung semiconductor, K9K1208Q0C Datasheet
K9K1208Q0C
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Document Title 64M x 8 Bit , 32M x 16 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 1.0 1.Pin assignment of TBGA dummy ball is changed. (before) DNU --> (after) N.C 2. Add the ,tf & ibusy graph for 1.8V device (Page 34) 3 ...
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... AC parameters are changed. tWC tWH tWP tRC tREH tRP tREA tCEA K9K12XXU0C K9K12XXD0C 50 15 K9K12XXQ0C parameters are changed. 2.8 tWC tWH tWP tRC tREH tRP tREA tCEA K9K1208Q0C 50 15 K9K1216Q0C The Test Condition for Stand-by Currents are changed. 2 CE=V , WP=0V/V SB ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C 64M x 8 Bit / 32M x 16 Bit NAND Flash Memory PRODUCT LIST. Part Number Vcc Range K9K1208Q0C-G,J 1.70 ~ 1.95V K9K1216Q0C-G,J K9K1208D0C-G,J 2.4 ~ 2.9V K9K1216D0C-G,J K9K1208U0C-G,J 2.7 ~ 3.6V K9K1216U0C-G,J FEATURES • Voltage Supply - 1.8V device(K9K12XXQ0C) : 1.70~1.95V - 2.65V device(K9F12XXD0C) : 2.4~2.9V - 3.3V device(K9K12XXU0C) : 2.7 ~ 3.6 V • Organization - Memory Cell Array ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C PIN CONFIGURATION (FBGA) K9K12XXX0C-GCB0,JCB0/GIB0,JIB0 N.C N.C A N.C /WP ALE Vss /CE /WE R /RE CLE LOCKPRE Vcc H NC I/O1 NC VccQ I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C (Top View) ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The (K9K1208X0C) O pins float to high-z when the chip is deselected or when the outputs are disabled. ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Figure 1-1. K9K1208X0C (X8) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9K1208X0C (X8) ARRAY ORGANIZATION 128K Pages ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Figure 1-2. K9K1216X0C (X16) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-2. K9K1216X0C (X16) ARRAY ORGANIZATION ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C PRODUCT INTRODUCTION The K9K12XXX0C is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buff- ers and memory during page read and page program operations ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9K12XXX0C-XCB0 Temperature Under Bias K9K12XXX0C-XIB0 K9K12XXX0C-XCB0 Storage Temperature K9K12XXX0C-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C DC AND OPERATING CHARACTERISTICS Parameter Symbol Sequential tRC=50ns, CE=V Operat Read I =0mA OUT ing Current Program Erase CE=V , WP=LOCKPRE=0V/V IH Stand-by Current(TTL Stand-by Cur CE=V -0.2, WP=LOCKPRE=0V rent(CMOS) Input Leakage Current Vcc(max ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C VALID BLOCK Parameter Symbol Valid Block Number N NOTE : device 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre- sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits factory-marked bad blocks ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C PROGRAM/ERASE CHARACTERISTICS Parameter Program Time Dummy Busy Time for the Lock or Lock-tight Block Number of Partial Program Cycles in the Same Page Block Erase Time AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT Parameter Symbol K9K1208X0C K9K12XXD0C K9K12XXU0C ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C AC CHARACTERISTICS FOR OPERATION Parameter Symbol Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay t Ready to RE Low RE Pulse Width WE High to Busy t Read Cycle Time RE Access Time t CE Access Time t RE High to Output Hi High to Output Hi-Z ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Pointer Operation of K9K1208X0C(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Pointer Operation of K9K1216X0C(X16) Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte(x8 device), 264word(x16 device) page registers are utilized as seperate buffers for this operation and the system design gets more flexible ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Device K9K1208X0C(X8 device) K9K1216X0C(X16 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. I/O8~15 are used only for data bus. Command Latch Cycle CLE t CLS ALS ALE I/Ox Address Latch Cycle t CLS CLE t CS ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 Serial Access Cycle after Read CE t REA RE I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Status Read Cycle CLE t CLS I/Ox READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address I/O 00h or 01h Column Address R/B X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Read1 Operation (Intercepted by CE) CLE CE WE ALE I/O 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE RE I/O 50h R/B M Address ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Page Program Operation CLE ALE RE I/O 80h Sequential Data Column Page(Row) Input Command Address R Din Din A 10h 527 528 Byte Data Program Command Serial Input ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Copy-Back Program Operation CLE ALE RE I/O 00h Column Page(Row) Address Address R/B BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE ALE RE I/O 60h Page(Row) Address ...
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... K9K1216U0C MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle REA 00h ECh Maker Code Device K9K1208Q0C K9K1208D0C K9K1208U0C K9K1216Q0C K9K1216D0C K9K1216U0C 26 FLASH MEMORY Device Code* Device Code Device Code* 36h 76h 76h XX46h XX56h XX56h ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Figure 9. Read2 Operation CLE CE WE ALE R/B RE I/Ox Start Add.(4Cycle) 50h X8 device : & X16 device : & device : Don’t care 4 7 X16 device : are "L" ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528 264 (X8 device) or (X16 device) ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup com- mand(60h). Only address valid while loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... Figure 14. RESET Operation R/B I/Ox FFh Table5. Device Status Operation Mode t CEA WHR1 REA ECh Maker code Device K9K1208Q0C K9K1208D0C K9K1208U0C K9K1216Q0C K9K1216D0C K9K1216U0C t RST After Power-up Read 1 Waiting for next command 31 FLASH MEMORY Device Code* Device code Device Code* 36h ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C > In high state of LOCKPRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded as NAND Flash without LOCKPRE pin. Block Lock Mode Block Lock mode is enabled while LOCKPRE pin state is high, which is to offer protection features for NAND Flash data. The Block Lock mode is divided into Unlock, Lock, Lock-tight operation ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C 2) Unlock - Command Sequence: Unlock block Command(23h) + Start block address + Command(24h) + End block address - Unlocked blocks can be programmed or erased unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate commands. - Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available. ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C WPx = H & Unlock block Command (23h) + Start Block Address unlock Block Lock reset WPx = H & WPx = L (>100ns) Lock block command (2Ah) WPx = H & Lock-tight block command (2Ch) Lock-tight Figure 15. State diagram of Block Lock Program/Erase OPERATION(In Locked or Lock-tighten Block) ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C 2. Block Lock Status Read Block Lock Status can be read on a block basis, which may be read to find out whether designated block is available to be pro- grammed or erased. After writing 7Ah command to the command register. and block address to be checked, a read cycle outputs the content of the Block Lock Status Register to the I/O pins on the falling edge RE, whichever occurs last ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. LOCKPRE pin controls activation of auto- page read function. Auto-page read function is enabled only when LOCKPRE pin is logic high state after power-on without latency ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance V (Max Rp(min, 1.8V part (Max Rp(min, 2.65V part (Max Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. ...
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... K9K1208Q0C K9K1216Q0C K9K1208D0C K9K1216D0C K9K1208U0C K9K1216U0C Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 18 ...