K9K1G08U0B Samsung semiconductor, K9K1G08U0B Datasheet
K9K1G08U0B
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K9K1G08U0B Summary of contents
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Document Title 128M x 8 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 0.1 1. Note 1 ( Program/Erase Characteristics) is added( page NAND Flash Technical Notes is changed. -Invalid block -> initial invalid block ( page 15 ) -Error in write or read operation ( page 16 ) -Program Flow Chart ( page Vcc range is changed -1.7V~1.95V -> ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B 128M x 8 Bit Bit NAND Flash Memory PRODUCT LIST Part Number K9K1G08R0B-G,J K9K1G08B0B-G,J K9K1G08U0B-G,J FEATURES • Voltage Supply - 1.8V device(K9K1G08R0B) : 1.65 ~ 1.95V - 2.7V device(K9K1G08B0B) : 2.5 ~ 2.9V - 3.3V device(K9K1GXXU0B) : 2.7 ~ 3.6 V • Organization - Memory Cell Array -128M + 4096K)bit x 8 bit - Data Register - (512 + 16)bit x 8bit • Automatic Program and Erase ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B PIN CONFIGURATION (FBGA) K9K1G08X0B-GCB0,JCB0/GIB0,JIB0 N.C N.C N.C N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE I/ Vcc NC I/O1 NC VccQ I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C N.C N.C N.C Top View 3 Advance FLASH MEMORY ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Top View 8.50 ±0.10 #A1 0.10MAX Bottom View 8.50 ±0.10 0. 7.20 0. 4.00 0. (Datum (Datum 63-∅0.45 ±0.05 ∅ 0. 2.00 Side View 13.50 ±0.10 0.45 ±0.05 4 Advance FLASH MEMORY #A1 INDEX MARK(OPTIONAL ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B PIN DESCRIPTION Pin Name I/O ~ I/O DATA INPUTS/OUTPUTS 0 7 (K9K1G08X0B) The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Figure 1-1. Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. Array Organization 256K Pages 1st half Page Register ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Product Introduction The K9K1G08X0B is a 1,026Mbit(1,107,296,436 bit) memory organized as 262,144 rows(pages) by 528 columns. Spare sixteen col- umns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Memory Map The device is arranged in eight 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory array into plane 0~3 or plane 4~7 separately ...
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... K9K1G08X0B-XIB0 T A K9K1G08B0B(2.7V) Typ. Max Min Typ. 1.8 1.95 2.5 2.7 1.8 1.95 2.5 2 Advance FLASH MEMORY Rating Unit 2.7V/3.3V Device -0 4 4.6 -0 4.6 -10 to +125 °C -40 to +125 °C -65 to +150 5 mA +2.0V for periods <20ns. CC =-40 to 85°C) A K9K1G08U0B(3.3V) Unit Max Min Typ. Max 2.9 2.7 3.3 3.6 V 2.9 2.7 3.3 3 ...
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... V K9K1G08B0B :I OL Level K9K1G08U0B :I K9K1G08R0B :V Output Low Current I (R/B) K9K1G08B0B :V (R/B) OL K9K1G08U0B :V NOTE : V can undershoot to -0.4V and V can overshoot Valid Block Parameter Symbol Valid Block Number N NOTE : 1. The device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre- sented with both cases of invalid blocks considered ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B AC TEST CONDITION (K9K1G08X0B-XCB0 :TA=0 to 70°C, K9K1G08X0B-XIB0 :TA=-40 to 85°C K9K1G08R0B : Vcc=1.65V~1.95V , K9K1G08B0B : Vcc=2.5V~2.9V, K9K1G08U0B : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels K9K1G08R0B:Output Load (Vcc :1.8V +/-10%) Q K9K1G08B0C:Output Load (Vcc :2 ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B AC Timing Characteristics for Command / Address / Data Input Parameter Symbol 1.8V CLE Set-up Time t 0 CLS CLE Hold Time t 10 CLH CE Setup Time Hold Time Pulse Width ALE Setup Time t 0 ALS ALE Hold Time ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Pointer Operation of K9K1G08X0B Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Device K9K1G08X0B Command Latch Cycle CLE ALS ALE I Address Latch Cycle t CLS CLE ALS ALE I I/O I/ CLH CLS ALH Command ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Input Data Latch Cycle CLE ALS WC ALE I/O ~ DIN Serial access Cycle after Read R/B NOTES : Transition is measured ±200mV from steady state voltage with load DIN 511 ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Status Read Cycle CLE t CLS I/O X Read1 Operation (Read One Page) CLE ALE 00h or 01h I Column Address R/B t CLR t CLH WHR 70h AR2 ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Read1 Operation (Intercepted by CE) CLE CE WE ALE I/O ~ 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE RE I/O ~ 50h R/B M Address Dout ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Page Program Operation CLE ALE RE I/O ~ 80h Sequential Data Column Input Command Address R/B BLOCK ERASE OPERATION CLE ALE RE I/O ~ 60h Page(Row) Address R/B Auto Block Erase Setup Command ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B ≈ ≈ FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 23 Advance ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7 CLE ALE RE I/O ~ 60h Page(Row) Address R/B Block Erase Setup Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. ...
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... Byte th t READ Device* 00h ECh Code Maker Code Device K9K1G08R0B K9K1G08B0B K9K1G08U0B Description Maker Code Device Code Must be don’t -cared Supports Multi Plane Operation (Must be don’t-cared for 1.8V device) 25 Advance FLASH MEMORY C0h A5h Multi Plane Code Device Code ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Copy-Back Program Operation CLE ALE RE I/O ~ 00h Column Page(Row) Address Address R 8Ah 25 Column Page(Row) Address Address Busy Copy-Back Data Input Command 26 Advance ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with four address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Figure 8. Read1 Operation CLE CE WE ALE R/B RE 00h Start Add.(4Cycle) I & After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle (00h Command) 1st half array ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Figure 9. Read2 Operation CLE CE WE ALE R/B RE 50h I/O ~ Start Add.(4Cycle & ′ Don t Care 1st half array 2nd half array Data Field Spare Field 29 Advance FLASH MEMORY Data Output(Sequential) Spare Field ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page with- out an intervening erase operation must not exceed 1 for main array and 2 for spare array ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Multi-Plane Page Program into Plane 0~3 or Plane 4~7 Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7 enables a simultaneous programming of four pages ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Restirction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the four least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 13 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure17. Figure 13. Multi-Plane Program & ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane Copy- Back programming of four pages. Partial activation of four planes is also permitted. ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B ≈ ≈ ≈ ≈ ≈ ≈ FLASH MEMORY 35 Advance ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... The command register remains in Read ID mode until further commands are issued to it. Figure 20 shows the operation sequence. Figure 20. Read ID Operation 1 CLE CE WE ALE RE I 90h 00h Address. 1cycle t CEA WHR t REA Device* ECh Code Maker code Device K9K1G08R0B K9K1G08B0B K9K1G08U0B 37 Advance FLASH MEMORY A5h C0h Multi-Plane code Device Code 78h 79h 79h ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Rp value guidance Rp(min, 1.8V part) = Rp(min, 2.7V part) = Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. L Rp(max) is determined by maximum permissible limit of tr ° Vcc = 1.8V Ibusy 300n 1.7 200n 0. 100n 0.57 1.7 1 Rp(ohm) ° ...
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... K9K1G08R0B K9K1G08B0B K9K1G08U0B Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 23 ...