EX256-FCS100 ETC1 [List of Unclassifed Manufacturers], EX256-FCS100 Datasheet - Page 13

• Manufacturer Part Number: EX256-FCS100
• Description: eX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

e X F a m il y F P GA s
eX T i m i n g M o de l *
*Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
H ar d-W i re d C loc k
External Setup = t
Clock-to-Out (Pad-to-Pad), typical
Hard-Wired
Routed
Clock
Clock
= t
= 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
I/O Module
I/O Module
= 0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
HCKH
INYH
t
t
Input Delays
INYH
INYH
t
HCKH
t
RCKH
(100% Load)
+ t
= 0.7 ns
= 0.7 ns
+ t
= 1.1 ns
IRD1
RCO
= 1.3 ns
+ t
+ t
SUD
RD1
t
t
t
t
t
IRD1
IRD2
IRD1
– t
+ t
t
t
SUD
HD
SUD
HD
HCKH
DHL
= 0.0 ns
= 0.0 ns
= 0.3 ns
= 0.4 ns
= 0.3 ns
= 0.5ns
= 0.5 ns
t
t
Register
Register
RCO
RCO
D
D
Cell
Cell
Internal Delays
Combinatorial
t
= 0.6 ns
= 0.6 ns
v3.0
PD
Cell
Q
Q
= 0.7 ns
Ro ute d C loc k
External Setup = t
Clock-to-Out (Pad-to-Pad), typical
t
t
RD1
RD1
= 0.3 ns
= 0.3 ns
t
t
t
RD1
RD4
RD8
Predicted
Routing
Delays
= 0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
= t
= 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
= 0.3 ns
= 0.7 ns
= 1.2 ns
INYH
RCKH
I/O Module
I/O Module
t
t
DHL
DHL
+ t
+ t
IRD2
I/O Module
t
= 2.6 ns
t
= 2.6 ns
RCO
ENZL
ENZL
Output Delays
+ t
+ t
= 1.9 ns
= 1.9 ns
t
DHL
SUD
RD1
= 2.6 ns
– t
+ t
RCKH
DHL
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