EX256-FCS100 ETC1 [List of Unclassifed Manufacturers], EX256-FCS100 Datasheet - Page 6

• Manufacturer Part Number: EX256-FCS100
• Description: eX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

operating conditions are reached. Please see the Actel SX-A
and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications application note for more information on hot
swapping.
P ower R equ ir em ent s
The eX family supports mixed voltage operation and is
designed to tolerate 5.0V inputs in each case
Power consumption is extremely low due to the very short
distances signals, which are required to travel to complete a
circuit. Power requirements are further reduced because of
the small number of low-resistance antifuses in the path.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power architecture FPGA available today. Also, when
the device is in low power mode, the clock pins must not
float. They must be driven either HIGH or LOW. We
recommend that signals driving the clock pins be fixed at
HIGH or LOW rather than toggle to achieve maximum power
efficiency.
Table 2 • Supply Voltages
Low P ower Mode
The new Actel eX family has been designed with a Low
Power Mode. This feature, activated with a special LP pin, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated when the device enters this mode.
Since the core of the device is turned off, the states of the
registers are lost. The device must be re-initialized when
normal operating mode is achieved.
2.5V LP/Sleep Mode Specifications
Typical Conditions, V
Bou ndar y S can T es ti ng (BS T )
All eX devices are IEEE 1149.1 compliant. eX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test pins
6
Product
eX64
eX128
eX256
eX128
eX256
eX64
Low Power Standby Current
V
2.5V
2.5V
2.5V
CCA
CCA
100
134
111
V
2.5V
3.3V
5.0V
, V
CCI
CCI
= 2.5V, T
Maximum
Tolerance
Input
5.0V
5.0V
5.0V
J
= 25 ° C
Maximum
Output
(Table
Drive
Units
2.5V
3.3V
5.0V
µA
µA
µA
2).
v3.0
in conjunction with the program fuse. The functionality of
each pin is described in
TCK, TDI, and TDO are dedicated pins and cannot be used
as regular I/Os. In flexible mode, TMS should be set HIGH
through a pull-up resistor of 10k Ω . TMS can be pulled LOW
to initiate the test sequence.
Table 3 • Boundary Scan Pin Functionality
C onfi gur ing Di agn ost i c P in s
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the “Variation” dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel's Designer software.
T RS T P i n
When the “Reserve JTAG Reset” box is checked, the TRST
pin will become a Boundary Scan Reset pin. In this mode,
the TRST pin will function as an asynchronous, active-low
input to initialize or reset the BST circuit. An internal
pull-up resistor will be automatically enabled on the TRST
pin.
The TRST pin will function as a user I/O when the “Reserve
JTAG Reset” box is not checked. The internal pull-up
resistor will be disabled in this mode.
D edic at ed T e st M ode
When the “Reserve JTAG” box is checked, the eX device is
placed in Dedicated Test mode, which configures the TDI,
TCK, and TDO pins for BST or in-circuit verification with
Silicon Explorer II. An internal pull-up resistor is
automatically enabled on both the TMS and TDI pins. In
Dedicated Test Mode, TCK, TDI, and TDO are dedicated test
pins and become unavailable for pin assignment in the Pin
Editor. The TMS pin will function as specified in the IEEE
1149.1 (JTAG) Specification.
Fl exi ble Mo de
When the “Reserve JTAG” box is not selected (default
setting in Designer software), eX is placed in Flexible mode,
which allows the TDI, TCK, and TDO pins to function as user
I/Os or BST pins. In this mode the internal pull-up resistors
on the TMS and TDI pins are disabled. An external 10k Ω
pull-up resistor to V
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
Program Fuse Blown
(Dedicated Test Mode)
TCK, TDI, TDO are
dedicated BST pins
No need for pull-up resistor
for TMS
CCI
is required on the TMS pin.
Table
3. In the dedicated test mode,
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are flexible
and may be used as I/Os
Use a pull-up resistor of
10k
Ω
on TMS
e X F a m il y F P GA s