EX256-FCS100 ETC1 [List of Unclassifed Manufacturers], EX256-FCS100 Datasheet - Page 7

• Manufacturer Part Number: EX256-FCS100
• Description: eX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

e X F a m il y F P GA s
machine reaches the “logic reset” state. At this point the
BST pins will be released and will function as regular I/O
pins. The “logic reset” state is reached five TCK cycles after
the TMS pin is set to logical HIGH.
The Program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
Dev el opm ent To ol S uppor t
The eX devices are fully supported by Actel’s line of FPGA
development tools, including the Actel Designer Series suite
and Libero, the FPGA design tool suite. Designer Series,
Actel’s suite of FPGA development tools for PCs and
Workstations, includes the ACTgen Macro Builder, timing
driven place-and-route, timing analysis tools, and fuse file
generation. Libero is a design management environment
that integrates the needed design tools, streamlines the
design flow, manages all design and log files, and passes
necessary design data between tools. Libero includes
Synplify, ViewDraw, Actel’s Designer Series, ModelSim HDL
Simulator, WaveFormer Lite, and Actel Silicon Explorer.
In addition, the eX devices contain internal probe circuitry
that provides built-in access to the output of every C-cell,
R-cell, and routed clock in the design, enabling 100-percent
real-time observation and analysis of a device's internal
logic nodes without design iteration. The probe circuitry is
accessed by Silicon Explorer II, an easy-to-use integrated
Figure 7 • Probe Setup
Serial Connection
Silicon Explorer II
v3.0
verification and logic analysis tool that can sample data at
100 MHz (asynchronous) or 66 MHz (synchronous). Silicon
Explorer II attaches to a PC’s standard COM port, turning
the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design
verification process at their desks and reduces verification
time from several hours per cycle to only a few seconds.
eX P ro be Cir cu it C ont ro l Pi ns
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation.
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification. The TRST pin is equipped
with an internal pull-up resistor. To remove the boundary
scan state machine from the reset state during probing, it is
recommended that the TRST pin be left floating.
De si gn C ons id era ti ons
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins
should not be used as input or bidirectional ports. Because
these pins are active during probing, critical signals input
through these pins are not available while probing. In
addition, the Security Fuse should not be programmed
because doing so disables the probe circuitry.
TMS
TDO
TCK
TDI
PRA
PRB
eX FPGA
Figure 7
illustrates the
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