EX256-FCS100 ETC1 [List of Unclassifed Manufacturers], EX256-FCS100 Datasheet - Page 5

• Manufacturer Part Number: EX256-FCS100
• Description: eX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

e X F a m il y F P GA s
Cl ock Res our ce s
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-Cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling the 3.9ns clock-to-out (pad-to-pad) performance of
the eX devices. The hard-wired clock is tuned to provide a
clock skew of less than 0.1ns worst case.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal
logic signals within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then
the external clock pin cannot be used for any other input
and must be tied low or high.
circuit used for the constant load HCLK.
the CLKA and CLKB circuit used in eX devices.
Figure 5 • eX HCLK Clock Pad
Figure 6 • eX Routed Clock Buffer
O t he r A r c hi t ec tu ral Fe atu r e s
T echno log y
Actel’s eX family is implemented on a high-voltage twin-well
CMOS process using 0.22 µ design rules. The metal-to-metal
antifuse is made up of a combination of amorphous silicon
and dielectric material with barrier metals and has an “on”
state resistance of 25 Ω with a capacitance of 1.0 fF for low
signal impedance.
P erf orm a nce
The combination of architectural features described above
enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution of
complex logic functions. Thus, the eX family is an optimal
HCLKBUF
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 5
Constant Load
Clock Network
From Internal Logic
describes the clock
Clock Network
Figure 6
describes
v3.0
platform upon which to integrate the functionality
previously contained in CPLDs. In addition, designs that
previously would have required a gate array to meet
performance goals can now be integrated into an eX device
with dramatic improvements in cost and time to market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
I / O M o d u l e s
Each I/O on an eX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even without
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(pad-to-pad) timing as fast as 3.9ns. I/O cells that have
embedded latches and flip-flops require instantiation in HDL
code; this is a design complication not encountered in eX
FPGAs. Fast pin-to-pin timing ensures that the device will
have little trouble interfacing with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time. See
more information.
Table 1 • I/O Features
Hot S wa ppin g
eX I/Os are configured to be hot swappable. During power
up/down (or partial up/down), all I/Os are tristated. V
and V
and they do not require a specific power-up or power-down
sequence in order to avoid damage to the eX devices. After
the eX device is plugged into an electrically active system,
the device will not degrade the reliability of or cause
damage to the host system. The device’s output pins are
driven to a high impedance state until normal chip
Function
Input Buffer
Threshold
Selection
Flexible
Output
Driver
Output
Buffer
Power Up
CCI
do not have to be stable during power up/down,
Description
Individually selectable pull ups and pull
• TTL/3.3V LVTTL
• 2.5V LVCMOS 2
• 3.3V LVTTL
• 5.0V TTL/CMOS
“Hot-Swap” Capability
• I/O on an unpowered device does not
• Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
downs during power up (default is to power
up in tristate)
Enables deterministic power up of device
V
CCA
sink current
and V
CCI
can be powered in any order
Table 1
CCA
for
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