EX256-FCS100 ETC1 [List of Unclassifed Manufacturers], EX256-FCS100 Datasheet - Page 15

• Manufacturer Part Number: EX256-FCS100
• Description: eX Family FPGAs
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

e X F a m il y F P GA s
C el l T i m i n g C h ar a c t er i st i c s
Ti m i ng C ha r a ct e r i s t i c s
Timing characteristics for eX devices fall into three
categories:
design-dependent.
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer utility or performing simulation with post-layout
delays.
Cr it ic al Net s and T ypi cal Ne ts
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to
six percent of the nets in a design may be designated as
critical.
Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s
( N or m ali z ed to W or st - Cas e Com m er ci al, T
Fl ip- Flo ps
PRESET
V
CLR
CLK
2.3
2.5
2.7
CCA
Q
D
family-dependent,
The
0.75
0.70
0.66
–55
t
SUD
input
device-dependent,
and
0.79
0.74
0.69
–40
output
t
t
CLK
HPWH
RPWH
(Positive edge triggered)
D
0.88
0.82
0.79
buffer
0
and
,
J
Junction Temperature (T
= 70 ° C, V
t
v3.0
HD
PRESET
CLR
t
RCO
Long T r acks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three to five antifuse
connections. This increases capacitance and resistance,
resulting in longer net delays for macros connected to long
tracks. Typically, no more than six percent of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout routing delays.
T im in g D er at ing
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
0.89
0.83
0.79
25
C C A
t
t
HPWL
RPWL
Q
= 2.3 V)
t
,
t
WASYN
CLR
J
1.00
0.93
0.88
)
70
t
HP
t
1.04
0.97
0.92
PRESET
85
1.16
1.08
1.02
125
15