NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 11

no-image

NT5DS16M16CS

Manufacturer Part Number
NT5DS16M16CS
Description
256Mb DDR Synchronous DRAM
Manufacturer
NANOAMP [NanoAmp Solutions, Inc.]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NT5DS16M16CS-5T
Manufacturer:
AD
Quantity:
291
Part Number:
NT5DS16M16CS-5T
Manufacturer:
NANYA
Quantity:
213
Part Number:
NT5DS16M16CS-5T
Manufacturer:
NANYA
Quantity:
2 526
Part Number:
NT5DS16M16CS-5T
Manufacturer:
NANYA
Quantity:
118
Part Number:
NT5DS16M16CS-5T
Manufacturer:
NANYA
Quantity:
8
Part Number:
NT5DS16M16CS-5T
Manufacturer:
NANYA
Quantity:
8 000
Part Number:
NT5DS16M16CS-5T
Manufacturer:
NANYA/南亚
Quantity:
20 000
Part Number:
NT5DS16M16CS-5TI
Manufacturer:
NANYA/南亚
Quantity:
20 000
Company:
Part Number:
NT5DS16M16CS-6K
Quantity:
1 400
NanoAmp Solutions, Inc.
Burst Definition
Notes:
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in Burst Definition on page 11.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Length
2
4
8
A2
0
0
0
0
1
1
1
1
Starting Column Address
A1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Sequential
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
1-0
0-1
Order of Accesses Within a Burst
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
Type = Interleaved
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
11

Related parts for NT5DS16M16CS