NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 61

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Electrical Characteristics & AC Timing - Absolute Specifications Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross; the
3. Inputs are not recognized as valid until V
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics
5. t
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate
10. For command/address input slew rate
11. CK/CK slew rates are
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
input reference level for signals other than CK/CK is V
(Note 3) is V
not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving
(LZ).
parameter, but system performance (bus turnaround) degrades accordingly.
CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the
device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic
LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this
time, depending on t
V
be guaranteed by design or tester characterization.
to the actual system clock cycle time. For example, for DDR266 at CL = 2.5, t
(20ns/7.5ns) = 2 + 3 = 5.
HZ
OL
and t
(AC).
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are
TT
.
DQSS
1.0V/ns.
.
0.5V/ns and < 1.0V/ns. Slew rate is measured between V
1.0V/ns. Slew rate is measured between V
REF
stabilizes.
REF
.
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
DAL
= (15ns/7.5ns) +
OH
(AC) and V
OH
OL
CK
(AC) and
(AC).
is equal
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