NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 59

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
Symbol
t
t
t
WPRES
t
DQSCK
t
t
t
t
t
DQSQ
t
WPRE
t
DQSS
DQSH
t
t
WPST
t
DIPW
DQSL
t
MRD
t
t
t
t
t
t
t
QHS
DSS
DSH
t
IPW
t
t
t
QH
t
t
AC
CH
CK
DH
DS
HZ
HP
CL
LZ
IH
IS
IH
IS
T
A
70 C V
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Input pulse width
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
DQS-DQ skew (DQS & associated DQ signals)
Minimum half clk period for any given cycle; defined by clk high
(t
Data output hold time from DQS
Data hold Skew Factor
Write command to 1st DQS latching
transition
DQS input high pulse width (write cycle)
DQS input low pulse width (write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
Address and control input setup time
(fast slew rate)
Address and control input hold time
(slow slew rate)
Address and control input setup time
(slow slew rate)
CH
) or clk low (t
DDQ
= V
DD
= 2.5V
CL
) time
0.2V (DDR333); V
Parameter
DDQ
CL = 2
CL = 2.5
CL=3
= V
DD
= 2.6V
0.1V (DDR400); See AC Characteristics)
t
(t
HP
CL
0.45
0.45
0.40
0.40
1.75
0.75
0.35
0.35
0.40
0.25
0.65
0.65
Min
min
2.2
0.2
0.2
0.6
0.6
0.65
0.55
0.65
0.65
12
- t
, t
5
5
0
-
QHS
CH
DDR400
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
(5T)
)
0.55
0.55
1.25
0.60
Max
0.5
0.65
0.55
12
0.65
0.65
0.40
8
-
t
(t
HP
CL
0.45
0.45
0.45
0.45
1.75
0.75
0.35
0.35
0.40
0.25
0.75
0.75
Min
min
2.2
0.2
0.2
0.8
0.8
0.70
0.60
12
- t
, t
6
6
0.7
0.7
0
-
(Part 1 of 2)
QHS
CH
DDR333
(6K)
)
Max
0.55
0.55
0.55
1.25
0.60
0.70
0.60
12
0.45
8
0.7
0.7
-
Unit
t
t
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
11, 12, 14
11, 12, 14
1-4, 15,
2-4, 10,
2-4, 10,
2-4, 12
15, 16
2-4, 9,
11, 12
2-4, 9,
11, 12
Notes
1-4, 5
1-4, 5
1-4, 7
1-4, 6
1-4,
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
16
59