NT5DS16M16CS NANOAMP [NanoAmp Solutions, Inc.], NT5DS16M16CS Datasheet - Page 46

• Manufacturer Part Number: NT5DS16M16CS
• Description: 256Mb DDR Synchronous DRAM
• Manufacturer: NANOAMP [NanoAmp Solutions, Inc.]

NanoAmp Solutions, Inc.
Power Down
Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all banks
are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in any bank, this
mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK, CK
and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the
DLL prior to entering Power Down. In that case, the DLL must be enabled after exiting Power Down, and 200 clock cycles must
occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at
the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, Power Down duration is limited by the
refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled Power
Down mode.
The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,
executable command may be applied one clock cycle later.
DOC # 14-02-044 Rev A ECN # 01-1116
The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com
Power Down
Command
CKE
CK
CK
No column
access in
progress
VALID
(Burst Read or Write operation
Enter Power Down mode
must not be in progress)
NOP
t
IS
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
power down
mode
NOP
Exit
t
IS
t
PDEX
VALID
Don’t Care
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