IS42S16100E-6BLI-TR ISSI, IS42S16100E-6BLI-TR Datasheet - Page 34

• Manufacturer Part Number: IS42S16100E-6BLI-TR
• Description: DRAM 16M 1Mx16 166Mhz SDRAM, 3.3v
• Manufacturer: ISSI

Specifications of IS42S16100E-6BLI-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 1 Mbit x 16
• Package / Case: BGA-60
• Memory Size: 16 Mbit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1000

34
IS42S16100E, IS45S16100E
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (t
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
COMMAND
COMMAND
wDl
) from the precharge command to the point
CLK
DQ
DQM
CLK
DQ
WRITE (CA=A, BANK 0)
WRITE A0
D
IN
WRITE (CA=A, BANK 0)
A0 D
D
WRITE A0
IN
IN
A0
A1 D
D
IN
A1
IN
A2
D
IN
D
IN
A2
t
A3
DPL
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (t
precharge command must be executed two clock cycles
after the input of the last burst data item.
PRECHARGE (BANK 0)
D
PRE 0
Integrated Silicon Solution, Inc. — www.issi.com
CAS Latency
IN
A3
t
MASKED BY DQM
t
wDl
Dpl
PRECHARGE (BANK 0)
t
WDL
PRE 0
=0
Dpl
) has elapsed. Therefore, the
3
0
2
2
0
2
05/18/2010
Rev. E