IS42S16100E-6BLI-TR ISSI, IS42S16100E-6BLI-TR Datasheet - Page 35

• Manufacturer Part Number: IS42S16100E-6BLI-TR
• Description: DRAM 16M 1Mx16 166Mhz SDRAM, 3.3v
• Manufacturer: ISSI

Specifications of IS42S16100E-6BLI-TR

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 1 Mbit x 16
• Package / Case: BGA-60
• Memory Size: 16 Mbit
• Maximum Clock Frequency: 166 MHz
• Access Time: 6 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 1000

IS42S16100E, IS45S16100E
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42/4516100E can output data continuously from
the burst start address (a) to location a+255 during a
read cycle in which the burst length is set to full page.
The IS42/4516100E repeats the operation starting at
the 256th cycle with the data output returning to location
(a) and continuing with a+1, a+2, a+3, etc. A burst stop
command must be executed to terminate this cycle. A
precharge command must be executed within the ACT
to PRE command period (t
stop command.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
05/18/2010
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
CLK
CLK
DQ
DQ
READ (CA=A, BANK 0)
READ (CA=A, BANK 0)
READ A0
READ A0
ras
max.) following the burst
D
OUT
A0 D
D
OUT
OUT
A0
A0 D
After the period (t
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (t
CAS latency is two and three clock cycle when the CAS
latency is three.
D
OUT
OUT
CAS Latency
A1
A0
BURST STOP
BURST STOP
t
rbD
D
D
OUT
OUT
BST
BST
A2
A1
rbD
rbD
) required for burst data output to
t
RBD
) is two clock cycle when the
D
D
OUT
OUT
t
RBD
A3
A2
3
3
D
OUT
HI-Z
A3
HI-Z
2
2
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