SSTU32864EC/G,551 NXP Semiconductors, SSTU32864EC/G,551 Datasheet - Page 11

• Manufacturer Part Number: SSTU32864EC/G,551
• Description: IC BUFFER 1.8V 25BIT SOT536-1
• Manufacturer: NXP Semiconductors

Specifications of SSTU32864EC/G,551

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935275429551; SSTU32864EC/G-S; SSTU32864EC/G-S

Philips Semiconductors
Table 7:
Recommended operating conditions; V
See
[1]
[2]
[3]
Table 8:
Recommended operating conditions; V
Class I, V
[1]
[2]
Table 9:
Recommended operating conditions, unless otherwise specified. V
9397 750 14092
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_
clock
W
ACT
INACT
su
h
MAX
PDM
PDMSS
PHL
This parameter is not necessarily production tested.
Data inputs must be active below a minimum time of t
Data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test-load transmission line delay.
This parameter is not necessarily production tested.
Figure 6
REF
Timing requirements
Switching characteristics
Output edge rates
through
= V
Parameter
clock frequency
pulse duration, CK, CK HIGH or
LOW
differential inputs active time
differential inputs inactive time
set-up time
hold time
Parameter
maximum input clock frequency
propagation delay
propagation delay, simultaneous
switching
propagation delay
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
TT
= V
Figure
DD
0.5 and C
11.
L
DD
DD
= 10 pF; unless otherwise specified. See
= 1.8 V
= 1.8 V
1.8 V configurable registered buffer for DDR2 RDIMM applications
Rev. 02 — 22 October 2004
0.1 V; T
Conditions
DCS before CK , CK ,
CSR HIGH
DCS before CK , CK ,
CSR LOW
CSR, ODT, CKE, and data
before CK , CK
DCS, CSR, ODT, CKE,
and data after CK , CK
0.1 V; T
Conditions
CK and CK to output
CK and CK to output
RESET to output
Conditions
ACT(max)
after RESET is taken HIGH.
amb
amb
= 0 C to +70 C; unless otherwise specified.
= 0 C to +70 C;
DD
= 1.8 V
INACT(max)
0.1 V
Figure 6
[1] [2]
[1] [3]
[1] [2]
[1]
after RESET is taken LOW.
Min
-
1
-
-
0.7
0.5
0.5
0.5
Min
450
1.41
-
-
Min
1
1
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
through
Typ
-
-
-
-
-
-
-
-
Typ
-
-
-
-
Typ
-
-
-
SSTU32864
Figure
11.
Max
450
-
10
15
-
-
-
-
Max
-
1.8
2.0
3
Max
4
4
1
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
Unit
V/ns
V/ns
V/ns
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