SSTU32864EC/G,551 NXP Semiconductors, SSTU32864EC/G,551 Datasheet - Page 6

• Manufacturer Part Number: SSTU32864EC/G,551
• Description: IC BUFFER 1.8V 25BIT SOT536-1
• Manufacturer: NXP Semiconductors

Specifications of SSTU32864EC/G,551

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-LFBGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935275429551; SSTU32864EC/G-S; SSTU32864EC/G-S

Philips Semiconductors
Table 2:
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[2]
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9397 750 14092
Product data sheet
Symbol
GND
V
V
ZOH
ZOL
CK
CK
C0, C1
RESET
CSR, DCS
D1 to D25
DODT
DCKE
Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B
QCS, QCSA,
QCSB
QODT, QODTA,
QODTB
QCKE, QCKEA,
QCKEB
n.c.
d.n.u.
DD
REF
Depends on configuration. Refer to
Configurations:
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
Configurations:
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Pin description
5.2 Pin description
Pin
B3, B4, D3, D4,
F3, F4, H3, H4, K3,
K4, M3, M4, P3,
P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6, G5
G2
J2, H2
A2, D2, G1
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Figure
Type
ground input
1.8 V nominal
0.9 V nominal
input
input
differential input
differential input
LVCMOS inputs
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
-
-
3,
Figure
1.8 V configurable registered buffer for DDR2 RDIMM applications
Rev. 02 — 22 October 2004
4, and
Figure 5
Description
ground
power supply voltage
input reference voltage
reserved for future use
reserved for future use
positive master clock input
negative master clock input
configuration control inputs
Asynchronous reset input. Resets registers and disables V
data and clock differential-input receivers.
Chip select inputs. Disables data outputs switching when both
inputs are HIGH.
Data inputs. Clocked in on the crossing of the rising edge of
CK and the falling edge of CK.
The outputs of this register will not be suspended by DCS and
CSR control.
The outputs of this register will not be suspended by DCS and
CSR control.
The outputs that are suspended by DCS and CSR control.
Data outputs that will not be suspended by DCS and CSR
control.
Data outputs that will not be suspended by DCS and CSR
control.
Data outputs that will not be suspended by DCS and CSR
control.
Not connected. Ball present but no internal connection to the
die.
Do-not-use. Ball internally connected to the die which should
be left open-circuit.
for ball number.
[2]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
SSTU32864
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REF
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