STM32F215RGT6TR STMicroelectronics, STM32F215RGT6TR Datasheet
STM32F215RGT6TR
Specifications of STM32F215RGT6TR
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STM32F215RGT6TR Summary of contents
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ARM-based 32-bit MCU, 150DMIPs Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features ■ Core: ARM 32-bit Cortex™-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™) ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32F21xxx 2.2.29 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 2.2.39 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 6 Package characteristics . . . . . . . . . . . . . . . . . . ...
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STM32F21xxx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 47. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table ...
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STM32F21xxx List of figures Figure 1. Compatible board design between STM32F10xx and STM32F2xx for LQFP64 package ...
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List of figures Figure 38. SPI timing diagram - slave mode and CPHA = ...
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STM32F21xxx in high-speed mode with external PHY ...
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... Introduction 1 Introduction This datasheet provides the description of the STM32F215xx and STM32F217xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the The STM32F215xx and STM32F217xx datasheet should be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F21x devices throughout the document ...
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STM32F21xxx 2 Description The STM32F21x family is based on the high-performance ARM core operating at a frequency 120 MHz. The family incorporates high-speed embedded memories (Flash memory Mbyte 128 Kbytes of system ...
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Table 2. STM32F215xx and STM32F217xx: features and peripheral counts Peripherals STM32F215Rx Flash memory in Kbytes 512 System SRAM in Kbytes Backup FSMC memory controller No (2) Ethernet General-purpose Advanced-control Timers Basic IWDG WWDG RTC Random number generator 2 SPI / ...
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Table 2. STM32F215xx and STM32F217xx: features and peripheral counts (continued) Peripherals STM32F215Rx Operating temperatures Package LQFP64 1. For the LQFP100 package, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip ...
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Description 2.1 Full compatibility throughout the family The STM32F215xx and STM32F217xx constitute the STM32F21x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom ...
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STM32F21xxx Figure 2. Compatible board design between STM32F10xx and STM32F2xx for LQFP100 package Two 0 Ω resistors connected to for the STM32F10xx - for the ...
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Description 2.2 Device overview Figure 4. STM32F21x block diagram NJTRST, JTDI, JTCK/SWCLK JTAG & SW JTDO/SWD, JTDO ETM TRACECLK TRACED[3:0] ARM Cortex-M3 120 MHz ART accelerator MII or RMII as AF Ethernet MAC MDIO as AF 10/100 USB DP, DM ...
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STM32F21xxx ® 2.2.1 ARM Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex-M3 processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, ...
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Description 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to ...
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STM32F21xxx 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer ...
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Description 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F21x devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M3. The NVIC ...
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STM32F21xxx 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: ● Boot from user Flash ● Boot from system memory ● Boot from embedded SRAM The boot loader is located in system ...
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Description Regulator ON The regulator ON modes are activated by default on LQFP packages. On UFBGA176 package, they are activated by connecting REGOFF minimum value is 1 There are three regulator ON modes: ● MR ...
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STM32F21xxx Figure 7. Startup in regulator OFF: fast V - power-down reset risen before V PDR=1.8 V 1.2 V 1.08 V 2.2.17 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F21x devices includes: ● The ...
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Description 2.2.18 Low-power modes The STM32F21x family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals ...
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STM32F21xxx 2.2.20 Timers and watchdogs The STM32F21x devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 3 compares the features of the advanced-control, general-purpose ...
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Description If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The TIM1 and TIM8 counters can be frozen in debug ...
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STM32F21xxx main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs free-running timer for application timeout management hardware- or ...
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Description Table 4. USART feature comparison USART Standard Modem LIN name features (RTS/CTS) USART1 X X USART2 X X USART3 X X UART4 X - UART5 X - USART6 X X 2.2.23 Serial peripheral interface (SPI) The STM32F21x devices feature ...
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STM32F21xxx 2.2.25 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer MHz in 8-bit mode, and ...
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Description 2.2.27 Controller area network (CAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames ...
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STM32F21xxx 2.2.30 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I achieve error-free I performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I disabling the main PLL (PLL) used for ...
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Description 2.2.32 Cryptographic acceleration The STM32F215xx and STM32F217xx devices embed a cryptographic accelerator. This cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to provide confidentiality, authentication, data integrity and non repudiation when exchanging ...
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STM32F21xxx 2.2.34 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down peripheral alternate function. ...
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Description 2.2.37 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 and 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used ...
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STM32F21xxx 3 Pinouts and pin description Figure 8. STM32F21x LQFP64 pinout PC13-RTC_AF1 PC14-OSC32_IN PC15-OSC32_OUT PH1-OSC_OUT VBAT PH0-OSC_IN 5 6 NRST ...
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Pinouts and pin description Figure 9. STM32F21x LQFP100 pinout VBAT PC13-RTC_AF1 PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 PH0-OSC_IN PH1-OSC_OUT NRST VDD_12 VSSA VREF+ VDDA PA0-WKUP 1. RFU means “reserved for future use”. This pin can be tied to V 36/173 PE2 1 ...
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STM32F21xxx Figure 10. STM32F21x LQFP144 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PC13-RTC_AF1 7 PC14-OSC32_IN 8 PC15-OSC32_OUT 9 PF0 10 PF1 11 PF2 12 PF3 13 PF4 14 PF5 SS_5 V ...
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Pinouts and pin description Figure 11. STM32F21x LQFP176 pinout PE2 1 PE3 2 PE4 3 PE5 4 PE6 5 VBAT 6 PI8-RTC_AF2 7 PC13-RTC_AF1 8 PC14-OSC32_IN 9 PC15-OSC32_OUT 10 PI9 11 PI10 12 PI11 SS_13 V 15 ...
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STM32F21xxx Figure 12. STM32F21x UFBGA176 ballout PE3 PE2 PE1 PE0 B PE4 PE5 PE6 PB9 C VBAT PI7 PI6 PI5 PC13- PI8- D PI9 PI4 TAMP1 TAMP2 PC14- E PF0 PI10 PI11 OSC32_IN PC15- ...
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Pinouts and pin description Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name - - - 7 D2 PI8 PC13 ( PC14 -OSC32_IN PC15 ...
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STM32F21xxx Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name PC0 PC1 PC2 PC3 - ...
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Pinouts and pin description Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name REGOFF PA4 ...
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STM32F21xxx Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name - - PF13 - - PF14 - - PF15 - - 56 66 ...
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Pinouts and pin description Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name - - - 83 M11 PH6 - - - 84 N12 PH7 - - - 85 M12 PH8 - - - 86 M13 PH9 - ...
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STM32F21xxx Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name - P14 PD9 - N15 PD10 - N14 PD11 - 59 81 100 N13 PD12 - 60 82 101 ...
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Pinouts and pin description Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name 117 G14 PC8 118 F14 PC9 41 67 100 119 F15 PA8 42 68 101 120 E15 PA9 43 ...
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STM32F21xxx Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name - - - 134 C13 - - - 135 D9 V SS_15 - - - 136 C9 V DD_15 49 76 109 137 A14 PA14 50 77 110 ...
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Pinouts and pin description Table 5. STM32F21x pin and ball definitions (continued) Pins Pin name - - 124 152 C10 PG9 - - 125 153 B10 PG10 - - 126 154 B9 PG11 - - 127 155 B8 PG12 - ...
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... Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, available from the STMicroelectronics website: www.st.com. ...
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Pinouts and pin description 7. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set internal Reset (active low). 8. FSMC_NL pin is also named FSMC_NADV on memory devices. 9. ...
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STM32F21xxx Table 6. FSMC pin definition (continued) Pins CF PE14 D11 PE15 D12 PD8 D13 PD9 D14 PD10 D15 PD11 PD12 PD13 PD14 D0 PD15 D1 PG2 PG3 PG4 PG5 PG6 PG7 PD0 D2 PD1 D3 PD3 PD4 NOE PD5 ...
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Table 7. Alternate function mapping AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PA0-WKUP TIM2_CH1_ETR TIM 5_CH1 TIM8_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 PA5 TIM2_CH1_ETR TIM8_CH1N PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN PA7 TIM1_CH1N ...
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Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PB14 TIM1_CH2N TIM8_CH2N PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N PC0 PC1 PC2 PC3 PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 PC9 MCO2 TIM3_CH4 ...
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Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PD14 TIM4_CH3 PD15 TIM4_CH4 PE0 TIM4_ETR PE1 PE2 TRACECLK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 TIM9_CH1 PE6 TRACED3 TIM9_CH2 PE7 TIM1_ETR PE8 TIM1_CH1N PE9 TIM1_CH1 ...
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Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PF15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 - OSC_IN PH1 - OSC_OUT PH2 PH3 ...
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Table 7. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PH14 TIM8_CH2N PH15 TIM8_CH3N PI0 TIM5_CH4 PI1 PI2 TIM8_CH4 PI3 TIM8_ETR PI4 TIM8_BKIN PI5 TIM8_CH1 PI6 TIM8_CH2 PI7 TIM8_CH3 PI8 PI9 PI10 PI11 AF4 AF5 ...
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STM32F21xxx 4 Memory mapping The memory map is shown in Figure 13. Doc ID 17050 Rev 8 Memory mapping 57/173 ...
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Memory mapping Figure 13. Memory map 0xFFFF FFFF 512-Mbyte block 7 Cortex-M3's internal 0xE000 0000 peripherals 0xDFFF FFFF 512-Mbyte block 6 Not used 0xC000 0000 0xBFFF FFFF 512-Mbyte block 5 FSMC registers 0xA000 0000 0x9FFF FFFF 512-Mbyte block 4 FSMC ...
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STM32F21xxx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...
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Electrical characteristics 5.1.6 Power supply scheme Figure 16. Power supply scheme 1.8-3 I/Os 2 × 2.2 μ 1/2/...14/15 15 × 100 × 4.7 μF 1/2/...14/15 REGOFF REF V REF+ 100 ...
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STM32F21xxx 5.1.7 Current consumption measurement Figure 17. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 9: Current characteristics, and permanent damage to the device. These are stress ratings only and functional ...
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Electrical characteristics Table 9. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...
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STM32F21xxx Table 11. General operating conditions (continued) Symbol Parameter V Internal core voltage to be supplied CAP1 externally in REGOFF mode V CAP2 Power dissipation suffix 105 °C for suffix 7 A ...
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Electrical characteristics Table 12. Limitations depending on the operating power supply range Maximum Operating power ADC supply operation range frequency (f 24 MHz with Conversion time up to 2.7 V memory wait 2 Msps 30 ...
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STM32F21xxx Figure 18. Number of wait states versus 5.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor to the VCAP1/VCAP2 pins. C Figure ...
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Electrical characteristics 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for T Table 14. Operating conditions at power-up / power-down (regulator ON) Symbol VDD V DD 5.3.4 Operating conditions at power-up ...
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STM32F21xxx 5.3.5 Embedded reset and power control block characteristics The parameters given in temperature and V Table 16. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (2) V PVD hysteresis PVDhyst Power-on/power-down V ...
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Electrical characteristics Table 16. Embedded reset and power control block characteristics (continued) Symbol Brownout level 1 V BOR1 threshold Brownout level 2 V BOR2 threshold Brownout level 3 V BOR3 threshold (2) V BOR hysteresis BORhyst (2)(3) T Reset temporization ...
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STM32F21xxx Typical and maximum current consumption The MCU is placed under the following conditions: ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled except explicitly mentioned. ● The ...
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Electrical characteristics Table 18. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM Symbol Parameter Supply current Run mode 1. Code and data processing running ...
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STM32F21xxx Figure 20. Typical current consumption vs temperature, Run mode, code with data processing running from RAM, and peripherals Figure 21. Typical current consumption vs temperature, Run mode, code with data processing ...
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Electrical characteristics Figure 22. Typical current consumption vs temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON 80.0 70.0 60.0 50.0 40.0 30.0 20.0 10.0 0.0 Figure 23. Typical current consumption vs temperature, Run ...
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STM32F21xxx Table 19. Typical and maximum current consumption in Sleep mode Symbol Parameter External clock all peripherals enabled Supply current Sleep mode External clock peripherals disabled 1. Based on characterization, tested in production External ...
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Electrical characteristics Figure 24. Typical current consumption vs temperature in Sleep mode, peripherals Figure 25. Typical current consumption vs temperature in Sleep mode, peripherals OFF ...
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STM32F21xxx Table 20. Typical and maximum current consumptions in Stop mode Symbol Parameter Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode with main Flash in Deep ...
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Electrical characteristics Table 21. Typical and maximum current consumptions in Standby mode Symbol Parameter Backup SRAM ON, low-speed oscillator and RTC ON Supply current Backup SRAM OFF, low Standby DD_STBY speed oscillator and RTC ON mode Backup SRAM ...
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STM32F21xxx ● At startup, all I/O pins are configured as analog inputs by firmware. ● All peripherals are disabled unless otherwise mentioned ● The given value is calculated by measuring the current consumption – with all peripherals clocked off – ...
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Electrical characteristics Table 23. Peripheral current consumption (continued) Peripheral APB1 78/173 (1) Typical consumption at 25 °C TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 SPI2 SPI3 CAN1 CAN2 (2) DAC channel ...
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STM32F21xxx Table 23. Peripheral current consumption (continued) Peripheral APB2 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in DAC_CR ...
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Electrical characteristics 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 25. High-speed external user clock ...
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STM32F21xxx Figure 27. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 28. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External clock ...
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Electrical characteristics Table 27. HSE 4-26 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F I HSE current consumption DD g Oscillator transconductance m (3) t Startup time SU(HSE 1. Resonator characteristics given by the crystal/ceramic resonator ...
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STM32F21xxx Table 28. LSE oscillator characteristics (f Symbol R Feedback resistor F I LSE current consumption DD g Oscillator Transconductance m (2) t startup time SU(LSE) 1. Guaranteed by design, not tested in production the startup time ...
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Electrical characteristics 5.3.9 Internal clock source characteristics The parameters given in ambient temperature and V High-speed internal (HSI) RC oscillator Table 29. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC HSI oscillator HSI oscillator (3) ...
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STM32F21xxx Low-speed internal (LSI) RC oscillator Table 30. LSI oscillator characteristics Symbol (2) f Frequency LSI (3) t LSI oscillator startup time su(LSI) (3) I LSI oscillator power consumption DD(LSI –40 to 105 ...
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Electrical characteristics Table 31. Main PLL characteristics (continued) Symbol Parameter t PLL lock time LOCK Cycle-to-cycle jitter Period Jitter (3) Jitter Main clock output (MCO) for RMII Ethernet Main clock output (MCO) for MII Ethernet Bit Time CAN jitter (4) ...
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STM32F21xxx Table 32. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Master I2S clock jitter (3) Jitter WS I2S clock jitter PLLI2S power consumption on (4) I DD(PLLI2S PLLI2S power consumption on (4) I DDA(PLLI2S) V DDA 1. Take ...
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Electrical characteristics 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 33. SSCG parameters constraint Symbol f Mod md MODEPER * INCSTEP 1. Guaranteed by design, not ...
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STM32F21xxx Figure 33 and Figure 34 down spread modes, where PLL_OUT T is the modulation period. mode md is the modulation depth. Figure 33. PLL output clock waveforms in center spread mode Frequency (PLL_OUT) Figure 34. PLL ...
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Electrical characteristics Table 35. Flash memory programming Symbol t Word programming time prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ME V ...
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STM32F21xxx Table 36. Flash memory programming with V Symbol Minimum current sunk the V Cumulative time during (3) t VPP which V 1. Guaranteed by design, not tested in production. 2. The maximum ...
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Electrical characteristics Table 38. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce a functional disturbance Fast transient voltage burst limits applied through 100 EFTB pins to ...
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STM32F21xxx Table 39. EMI characteristics Symbol Parameter package, conforming to SAE J1752/3 EEMBC, code running with ART enabled S Peak level EMI = 3 package, conforming to SAE J1752/3 EEMBC, ...
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Electrical characteristics Table 41. Electrical sensitivities Symbol Parameter LU Static latch-up class 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below V above V (for standard, 3 V-capable I/O ...
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STM32F21xxx 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 43. I/O static characteristics Symbol Parameter V Input low level voltage IL (2) TT I/O input high ...
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Electrical characteristics All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, ...
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STM32F21xxx 4. Based on characterization data, not tested in production. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 45, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and ...
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Electrical characteristics Table 45. I/O AC characteristics OSPEEDRy [1:0] bit Symbol (1) value F Maximum frequency max(IO)out 11 Output high to low level fall t f(IO)out time Output low to high level rise t r(IO)out time Pulse width of external ...
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STM32F21xxx 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology connected to a permanent pull-up resistor, R (see PU Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table ...
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Electrical characteristics 5.3.18 TIM timer characteristics The parameters given in Refer to Section 5.3.16: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 47. Characteristics of TIMx connected to the APB1 domain Symbol t Timer ...
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STM32F21xxx Table 48. Characteristics of TIMx connected to the APB2 domain Symbol t Timer resolution time res(TIM) Timer external clock f EXT frequency on CH1 to CH4 Res Timer resolution TIM 16-bit counter clock period t when internal clock is ...
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Electrical characteristics 2 Table 49 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...
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STM32F21xxx 2 Figure 37 bus AC waveforms and measurement circuit I²C bus S TART SDA t f(SDA) t h(STA) SCL t w(SCLH) 1. Measurement points are done at CMOS levels: 0.3V Table 50. SCL frequency ( ...
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Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.16: I/O port characteristics function characteristics ...
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STM32F21xxx Figure 38. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure 39. ...
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Electrical characteristics Figure 40. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 106/173 t c(SCK) t w(SCKH) t w(SCKL) MS BIN BI ...
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STM32F21xxx 2 Table 52 characteristics Symbol Parameter clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( valid time v(WS) ( hold ...
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Electrical characteristics 2 Figure 41 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first ...
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STM32F21xxx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Spee the USB OTG HS and USB OTG FS controllers. Table 53. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested in ...
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Electrical characteristics Figure 43. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines V CRS Table 55. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time ...
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STM32F21xxx Figure 44. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) Table 58. ULPI timing Symbol Control in (ULPI_DIR) setup time t SC Control in (ULPI_NXT) setup time t Control in ...
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Electrical characteristics Figure 45. Ethernet SMI timing diagram ETH_MDC ETH_MDIO(O) ETH_MDIO(I) Table 60. Dynamics characteristics: Ethernet MAC signals for SMI Symbol t MDC cycle time (2.38 MHz) MDC t MDIO write data valid time d(MDIO) t Read data setup time ...
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STM32F21xxx Table 62 gives the list of Ethernet MAC signals for MII and corresponding timing diagram. Figure 47. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] Table 62. Dynamics characteristics: Ethernet MAC signals for MII Symbol t ...
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Electrical characteristics 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in performed under the ambient temperature, f conditions summarized in Table 63. ADC characteristics Symbol Parameter V Power supply DDA V Positive reference voltage REF+ f ADC clock ...
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STM32F21xxx Table 63. ADC characteristics (continued) Symbol Parameter Sampling rate ( MHz) ADC ADC V DC current (2) REF I VREF+ consumption in conversion mode ADC VDDA DC current (2) I VDDA consumption in conversion ...
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Electrical characteristics 1. Better performance could be achieved in restricted V 2. Based on characterization, not tested in production. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this ...
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STM32F21xxx Figure 49. Typical connection diagram using the ADC R AIN (1) V AIN 1. Refer to Table represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the parasitic pad capacitance (roughly ...
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Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 50. Power supply and reference ...
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STM32F21xxx 5.3.21 DAC electrical characteristics Table 65. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (1) R Resistive load with buffer ON LOAD Impedance output with buffer ( OFF ...
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Electrical characteristics Table 65. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (3) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error ...
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STM32F21xxx Figure 52. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The ...
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Electrical characteristics 5.3.24 Embedded reference voltage The parameters given in temperature and V Table 68. Embedded internal reference voltage Symbol V Internal reference voltage REFINT ADC sampling time when (1) T reading the internal reference S_vrefint voltage Internal reference voltage ...
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STM32F21xxx Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_NE low ...
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Electrical characteristics Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:0] FSMC_NBL[1:0] FSMC_D[15:0] FSMC_NADV 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NE ...
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STM32F21xxx Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms FSMC_NE FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 71. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low time ...
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Electrical characteristics Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 72. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...
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STM32F21xxx Synchronous waveforms and timings Figure 57 through Table 76 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ● ...
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Electrical characteristics Table 73. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x=0..2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x= 0…2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low d(CLKL-NADVL) t FSMC_CLK ...
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STM32F21xxx Figure 58. Synchronous multiplexed PSRAM write timings FSMC_CLK FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:16] FSMC_NWE t d(CLKL-ADV) FSMC_AD[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL Table 74. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) ...
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Electrical characteristics Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) Table 75. Synchronous non-multiplexed NOR/PSRAM ...
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STM32F21xxx Figure 60. Synchronous non-multiplexed PSRAM write timings t w(CLK) FSMC_CLK t d(CLKL-NExL) FSMC_NEx t d(CLKL-NADVL) FSMC_NADV FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) FSMC_NBL Table 76. Synchronous non-multiplexed PSRAM write timings Symbol t FSMC_CLK period w(CLK) ...
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Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 61 through Table 78 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime ...
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STM32F21xxx Figure 62. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID 17050 Rev ...
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Electrical characteristics Figure 63. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 134/173 t v(NCE4_1-A) High ...
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STM32F21xxx Figure 64. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 65. PC Card/CompactFlash controller waveforms ...
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Electrical characteristics Figure 66. PC Card/CompactFlash controller waveforms for I/O space write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NWE FSMC_NOE FSMC_NIORD t d(NCE4_1-NIOWR) FSMC_NIOWR FSMC_D[15:0] Table 77. Switching characteristics for PC Card/CF read and write cycles in attribute/common space Symbol t ...
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STM32F21xxx Table 78. Switching characteristics for PC Card/CF read and write cycles in I/O space Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low to FSMC_NIOWR ...
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Electrical characteristics Figure 67. NAND controller waveforms for read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] Figure 68. NAND controller waveforms for write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] 138/173 t t d(ALE-NOE) ...
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STM32F21xxx Figure 69. NAND controller waveforms for common memory read access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Figure 70. NAND controller waveforms for common memory write access FSMC_NCEx ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE FSMC_NOE FSMC_D[15:0] Table 79. Switching ...
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Electrical characteristics Table 80. Switching characteristics for NAND Flash write cycles Symbol t FSMC_NWE low width w(NWE) t FSMC_NWE low to FSMC_D[15-0] valid v(NWE-D) t FSMC_NWE high to FSMC_D[15-0] invalid h(NWE-D) t FSMC_D[15-0] valid before FSMC_NWE high d(D-NWE) t FSMC_ALE ...
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STM32F21xxx Figure 72. SD default mode Table 82 MMC characteristics Symbol Clock frequency in data transfer f PP mode - SDIO_CK/f t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time r ...
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Package characteristics 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...
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STM32F21xxx Figure 73. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. Table 84. LQFP64 – pin low-profile quad flat package mechanical data ...
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Package characteristics Figure 74. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. Figure 75. LQFP100 100-pin low-profile quad flat package outline b Pin 1 identification 1. Drawing is not to scale. ...
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STM32F21xxx Table 85. LQPF100 – 100-pin low-profile quad flat package mechanical data Symbol Min A A1 0.050 A2 1.350 b 0.170 c 0.090 D 15.800 D1 13.800 D3 E 15.80v E1 13.800 0.450 ...
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Package characteristics Figure 77. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane 1. Drawing is not to scale. Table 86. LQFP144 mm, 144-pin low-profile quad flat package mechanical data Symbol Min A ...
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STM32F21xxx Figure 78. Recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 108 109 0.35 0.5 19.9 144 1 19.9 22.6 Doc ID 17050 Rev 8 Package characteristics 1. 17.85 22 ai14905c ...
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Package characteristics Figure 79. LQFP176 - Low profile quad flat package 24 × 24 × 1.4 mm, package outline C Seating plane Pin 1 identification 1. Drawing is not to scale. Table 87. LQFP176 - Low profile quad flat package ...
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STM32F21xxx Figure 80. LQFP176 recommended footprint 1. Dimensions are expressed in millimeters. 176 21.8 26.7 Doc ID 17050 Rev 8 Package characteristics 1.2 133 0.5 132 0 1.2 1T_FP_V1 149/173 ...
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Package characteristics Figure 81. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Seating plane BOTTOM VIEW 1. Drawing is not to scale. Table ...
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STM32F21xxx 6.2 Thermal characteristics The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ is the package junction-to-ambient thermal resistance, in °C/W, ● JA ● P max is ...
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Part numbering 7 Part numbering Table 90. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 215 = STM32F21x, connectivity, cryptographic acceleration 217= STM32F21x, connectivity, camera interface, cryptographic acceleration, Ethernet Pin ...
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STM32F21xxx Appendix A Application block diagrams A.1 Main applications versus package Table 91 gives examples of configurations for each package. Table 91. Main applications versus package for STM32F2xxx microcontrollers (1) 64 pins Config Config 1 2 OTG - - USB ...
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Application block diagrams A.2 Application example with regulator OFF Figure 82. Regulator OFF/internal reset ON Power-down reset risen after VCAP_1/VCAP_2 stabilization Application reset signal (optional (1.8 to 3.6 V) PA0 VDD REGOFF 1.2 V VCAP_1 VCAP_2 1. This ...
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STM32F21xxx Figure 84. USB OTG FS (full speed) host-only connection 1. The current limiter is required only if the application has to support a V switch can be used are available on the application board. 2. The ...
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Application block diagrams A.4 USB OTG high speed (HS) interface solutions Figure 86. OTG HS (high speed) device connection, host and dual-role in high-speed mode with external PHY STM32F20xxx USB HS OTG Ctrl ULPI PLL possible to ...
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STM32F21xxx A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 87 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% error maximum, ...
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Application block diagrams Figure 89. Audio player solution using PLL, PLLI2S, USB and 1 crystal XTAL 25 MHz or 14.7456 MHz MCO1PRE MCO1/ MCO2PRE MCO2 MCLK in Figure 90. Audio PLL (PLLI2S) providing accurate I2S clock 1 MHz CLKIN /M ...
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STM32F21xxx Figure 91. Master clock (MCK) used to drive the external audio DAC I2S_CK /I2SD 2,3,4,..,129 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 92. Master clock (MCK) not ...
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Application block diagrams A.6 Ethernet interface solutions Figure 93. MII mode using a 25 MHz crystal MCU HCLK (1) Timer input trigger TIM2 XTAL OSC 25 MHz 1. f must be greater than 25 MHz. HCLK 2. Pulse per second ...
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STM32F21xxx Figure 95. RMII with a 25 MHz crystal and PHY with PLL MCU HCLK (1) TIM2 2 MHz XTAL OSC 25 MHz 1. f must be greater than 25 MHz. HCLK 2. The 25 MHz (PHY_CLK) must ...
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Revision history 8 Revision history Table 92. Document revision history Date Revision 02-Feb-2010 13-Jul-2010 162/173 1 Initial release. Updated datasheet status to PRELIMINARY DATA. Renamed high-speed SRAM, system SRAM. Added UFBGA176 package, and note 1 related to LQFP176 package in ...
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STM32F21xxx Table 92. Document revision history (continued) Date Revision 25-Nov-2010 Added WLCSP66 (64+2) package. Added note 1 related to LQFP176 on cover page. Update I/Os in Section : Features. Updated Table 5: Multi-AHB Added case of BOR inactivation using IRROFF ...
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Revision history Table 92. Document revision history (continued) Date Revision 22-Apr-2011 164/173 Changed datasheet status to “Full Datasheet”. APB1 frequency changed form 36 MHz to 30 MHz. Introduced concept of SRAM1 and SRAM2. LQFP176 now in production. Removed WLCSP64+2 package. ...
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STM32F21xxx Table 92. Document revision history (continued) Date Revision 22-Apr-2011 (continued) Updated Typical and maximum current consumption well as Table 17: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) ...
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Revision history Table 92. Document revision history (continued) Date Revision 22-Apr-2011 (continued) 166/173 Updated t in Table 47: Characteristics of TIMx connected to the res(TIM) APB1 domain. Modified t res(TIM) TIMx connected to the APB2 Changed w(SCKH) ...
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STM32F21xxx Table 92. Document revision history (continued) Date Revision 14-Jun-2011 Added SDIO in Table 2: STM32F215xx and STM32F217xx: features and peripheral counts. Updated V for 5V tolerant pins in IN Updated jitter parameters description in characteristics. Remove jitter values for ...
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Revision history Table 92. Document revision history (continued) Date Revision 20-Dec-2011 168/173 Updated SDIO register addresses in Updated Figure 3: Compatible board design between STM32F10xx and STM32F2xx for LQFP144 design between STM32F10xx and STM32F2xx for LQFP100 Figure 1: Compatible board ...
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STM32F21xxx Table 92. Document revision history (continued) Date Revision 20-Dec-2011 (continued) Appendix A.3: USB OTG full speed (FS) interface Figure 84: USB OTG FS (full speed) host-only connection Note 2, updated Figure 85: OTG FS (full speed) connection dual-role with ...
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Revision history Table 92. Document revision history (continued) Date Revision 24-Apr-2012 170/173 Updated number of USB OTG HS and FS, added FSMC and Note 3 related to SPI/I2S in STM32F217xx: features and peripheral Added Note 2 and update TIM5 in ...
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STM32F21xxx Table 92. Document revision history (continued) Date Revision 29-Oct-2012 Removed Figure 4. Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated number of AHB buses in Section 2.2.12: Clocks and Updated Note 2 below Figure 4: STM32F21x ...
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Revision history Table 92. Document revision history (continued) Date Revision 29-Oct-2012 (continued) 172/173 Added Figure 80: LQFP176 recommended Added Note 2 below Figure 82: Regulator OFF/internal reset 8 Updated device subfamily in Remove reference to note 2 for USB IOTG ...
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