STM32F215RGT6TR STMicroelectronics, STM32F215RGT6TR Datasheet - Page 154

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STM32F215RGT6TR

Manufacturer Part Number
STM32F215RGT6TR
Description
ARM Microcontrollers - MCU STM32F21 High-Perf M3 1Mb 120 MHz MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32F215RGT6TR

Product Category
ARM Microcontrollers - MCU
Core
ARM Cortex M3
Data Bus Width
32 bit

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0
Application block diagrams
A.2
Figure 82. Regulator OFF/internal reset ON
1. This mode is available only on UFBGA176.
2. In regulator bypass mode, PA0 is used as power-on reset. The connection between PA0 and NRST can consequently
A.3
154/173
(1.8 to 3.6 V)
prevent debug connection. If the debug connection under reset or pre-reset is required, the user must manage the reset
and the power-on reset separately.
V DD
1.2 V
after VCAP_1/VCAP_2 stabilization
Application example with regulator OFF
USB OTG full speed (FS) interface solutions
Figure 83. USB OTG FS (full speed) device-only connection
1. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance
thanks to the large Rx/Tx FIFO and to a dedicated DMA controller.
Power-down reset risen
Application reset signal
VDD
REGOFF
VCAP_1
VCAP_2
PA0
(optional)
OSC_IN
OSC_OUT
STM32F20xxx
NRST
Doc ID 17050 Rev 8
V
PA9
PA11
PA12
DD
(1.8 to 3.6 V)
V DD
1.2 V
V CAP_1/2 monitoring
Ext. reset controller active
when V CAP_1/2 < 1.08 V
before VCAP_1/VCAP_2 stabilization
5V to V
Volatge regulator
Power-down reset risen
DD
VDD
REGOFF
VCAP_1
VCAP_2
PA0
(1)
Application reset
signal (optional)
IRROFF
NRST
VBUS
V
DM
DP
SS
STM32F21xxx
ai17295
ai18476

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