XRT83L38ES Exar, XRT83L38ES Datasheet - Page 2

• Manufacturer Part Number: XRT83L38ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
FEATURES
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F
IGURE
Fully integrated eight channel long-haul or short-haul transceivers for E1,T1 or J1 applications
Adaptive Receive Equalizer for up to 36dB cable attenuation
Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces
Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform
generator for transmit output pulse shaping available for both T1 and E1 modes
Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps
Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz
Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for
E1 and 0 to 3dB of cable attenuation for T1 modes
Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω (J1) applications
Internal and/or external impedance matching for 75Ω, 100Ω, 110Ω and 120Ω
Tri-State transmit output and receive input capability for redundancy applications
Provides High Impedance for Tx and Rx during power off
Transmit return loss meets or exceeds ETSI 300-166 standard
On-chip digital clock recovery circuit for high input jitter tolerance
Crystal-less digital jitter attenuator with 32-bit or 64-bit FIFO selectable either in transmit or receive path
On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources
High receiver interference immunity
On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO)
Receive loss of signal (RLOS) output
TNEG_n/CODES_n
RPOS_n/RDATA_n
TPOS_n/TDATA_n
RNEG_n/LCV_n
CLKSEL[2:0]
2. B
HW/HOST
TERSEL1
TERSEL0
MCLKE1
MCLKT1
RCLK_n
RLOS_n
TCLK_n
RXRES1
RXRES0
RXTSEL
TXTSEL
GAUGE
JASEL1
JASEL0
LOCK
D
IAGRAM OF THE
One of Eight Channels, CHANNEL_n - (n=0 : 7)
QRSS ENABLE
MASTER CLOCK SYNTHESIZER
GENERATOR
DETECTOR
DETECTOR
NETWORK
PATTERN
QRSS
LOOP
QRSS
ENCODER
DECODER
NLCD ENABLE
HDB3/
HDB3/
B8ZS
B8ZS
XRT83L38 T1/E1/J1 LIU (H
LOOPBACK
REMOTE
DETECTOR
LOS
ATTENUATOR
ATTENUATOR
TX/RX JITTER
TX/RX JITTER
HARWARE CONTROL
2
LOOPBACK
DETECTOR
DIGITAL
AIS
CONTROL
RECOVERY
TIMING &
TIMING
ARDWARE
DATA
LOOPBACK
ENABLE
EQUALIZER
CONTROL
TX FILTER
& PULSE
SHAPER
M
DETECTOR
& SLICER
LBO[3:0]
ODE
PEAK
DFM
)
LINE
DRIVER
EQUALIZER
LOOPBACK
MONITOR
ANALOG
LOCAL
DRIVE
RX
TEST
RTIP_n
RRING_n
LOOP1_n
LOOP0_n
MCLKOUT
TAOS_n
DMO_n
TTIP_n
TRING_n
TXON_n
ICT
RESET
TRATIO
SR/DR
EQC[4:0]
TCLKE
RCLKE
RXMUTE
ATAOS
REV. 1.0.2