XRT83L38ES Exar, XRT83L38ES Datasheet - Page 70

• Manufacturer Part Number: XRT83L38ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

XRT83L38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and
the Master Clock Rate in register 0x81h. Therefore, if the clock selection bits or the MCLRATE bit are being
programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is
important to "Not" write to any other bit location within the same register while selecting the input/output clock
frequency. For best results, register 0x81h can be broken down into two sub-registers with the MSB being bits
D[7:3] and the LSB being bits D[2:0] as shown in
F
Programming Examples:
Example 1: Changing bits D[7:3]
If bits D[7:3] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[2:0]
If bits D[2:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection (MSB) and then change bits D[2:0] (LSB) on the SECOND write, or vice-
versa. No order or sequence is necessary.
R
IGURE
EGISTER
10000001
B
25. R
D7
IT
A
#
DDRESS
EGISTER
Reserved
0
N
X
T
AME
81
D7
ABLE
H
S
36: M
UB
D6
Clock Selection Bits
R
EGISTERS
ICROPROCESSOR
MSB
D5
Figure
D4
R
67
EGISTER
F
25. Note: Bit D[7] is a reserved bit.
D3
UNCTION
#129, B
D2
ExLOS, ICT
IT
LSB
D
D1
ESCRIPTION
D0
R
EGISTER
T
R/W
YPE
REV. 1.0.2
R
V
ALUE
ESET
0