XRT83L38ES Exar, XRT83L38ES Datasheet - Page 33

• Manufacturer Part Number: XRT83L38ES
• Description: Peripheral Drivers & Components - PCIs
• Manufacturer: Exar

Specifications of XRT83L38ES

• Product Category: Peripheral Drivers & Components - PCIs
• Rohs: yes

REV. 1.0.2
The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING
outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the
transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding
DMO pin goes “High” and remains “High” until a valid transmit pulse is detected. In Host mode, the failure of
the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any
transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both
Hardware and Host modes on a per channel basis.
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT
The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the
shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a
tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the
transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the
state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode
transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip
supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform
generator for arbitrary transmit output pulse shapes (The arbitrary pulse generators are available for both T1
and E1). Transmit Line Build-Outs for T1 long-haul application are supported from 0dB to -22.5dB in three
7.5dB steps. The choice of the transmit pulse shape and LBO under the control of the interface bits are
summarized in
to-Customer Installation specification, Annex-E.
N
OTE
EQC4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
: EQC[4:0] determine the T1/E1 operating mode of the XRT83L38. When EQC4 = “1” and EQC3 = “1”, the XRT83L38
is in the E1 mode, otherwise it is in the T1/J1 mode. For details on how to enable the E1 arbitrary mode, see global
register 0xC0h.
EQC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
T
Table
ABLE
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
EQC2
5. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-
5: R
0
0
0
0
1
1
1
1
0
0
0
0
1
1
ECEIVE
EQC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
E
QUALIZER
EQC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C
ONTROL AND
E1/T1 M
T1 Short Haul/15dB
T1 Short Haul/15dB
T1 Short Haul/15dB
T1 Short Haul/15dB
T1 Short Haul/15dB
T1 Short Haul/15dB
T1 Long Haul/36dB
T1 Long Haul/36dB
T1 Long Haul/36dB
T1 Long Haul/36dB
T1 Long Haul/45dB
T1 Long Haul/45dB
T1 Long Haul/45dB
T1 Long Haul/45dB
S
ENSITIVITY
30
ODE
& R
T
RANSMIT
ECEIVE
L
133-266 ft./ 1.2dB
266-399 ft./ 1.8dB
399-533 ft./ 2.4dB
533-655 ft./ 3.0dB
INE
T
0-133 ft./ 0.6dB
Arbitrary Pulse
RANSMIT
B
-22.5dB
-22.5dB
-7.5dB
-7.5dB
-15dB
-15dB
UILD
0dB
0dB
-O
LBO
UT
S
ETTINGS
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
100 Ω / TP
C
ABLE
XRT83L38
C
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
B8ZS
ODING