PCF8576DT/S400/2,1 NXP Semiconductors, PCF8576DT/S400/2,1 Datasheet - Page 17

• Manufacturer Part Number: PCF8576DT/S400/2,1
• Description: LCD Drivers 2.64KHz 50mA 400mW
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT/S400/2,1

• Rohs: yes
• Maximum Clock Frequency: 2.64 kHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Package / Case: TSSOP-56
• Maximum Power Dissipation: 400 mW
• Maximum Supply Current: 50 mA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2000

NXP Semiconductors
PCF8576D
Product data sheet
7.5.1 Internal clock
7.5.2 External clock
7.5 Oscillator
7.6 Timing
7.7 Display register
7.8 Segment outputs
The internal logic of the PCF8576D and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin V
as the clock signal for several PCF8576Ds in the system that are connected in cascade.
Pin CLK is enabled as an external clock input by connecting pin OSC to V
frame signal frequency is determined by the clock frequency (f
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
The PCF8576D timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCF8576D in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
clock:
The display latch holds the display data while the corresponding multiplex signals are
generated.
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
f
fr
=
f
-------
24
clk
All information provided in this document is subject to legal disclaimers.
SS
.
. If the internal oscillator is used, the output from pin CLK can be used
Rev. 13 — 10 May 2012
Universal LCD driver for low multiplex rates
clk
).
PCF8576D
© NXP B.V. 2012. All rights reserved.
DD
. The LCD
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