PCF8576DT/S400/2,1 NXP Semiconductors, PCF8576DT/S400/2,1 Datasheet - Page 29

• Manufacturer Part Number: PCF8576DT/S400/2,1
• Description: LCD Drivers 2.64KHz 50mA 400mW
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT/S400/2,1

• Rohs: yes
• Maximum Clock Frequency: 2.64 kHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Package / Case: TSSOP-56
• Maximum Power Dissipation: 400 mW
• Maximum Supply Current: 50 mA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2000

NXP Semiconductors
PCF8576D
Product data sheet
8.4 I
8.5 Input filters
8.6 I
The PCF8576D acts as an I
transmit data to an I
the acknowledge signals of the selected devices. Device selection depends on the
I
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to V
applications A0, A1, and A2 are tied to V
no two devices with a common I
subaddress.
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Two I
PCF8576D. The entire I
Table 16.
The PCF8576D is a write-only device and will not respond to a read access, therefore bit
0 should always be logic 0. Bit 1 of the slave address byte that a PCF8576D will respond
to, is defined by the level tied to its SA0 input (V
Having two reserved slave addresses allows the following on the same I
The I
condition (S) from the I
slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I
ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.
Bit
2
2
2
C-bus slave address, on the transferred command data and on the hardware
•
•
C-bus controller
C-bus protocol
Up to 16 PCF8576D for very large LCD applications
The use of two types of LCD multiplex drive
2
2
C-bus protocol is shown in
C-bus slave addresses (0111 000 and 0111 001) are used to address the
Slave address
7
MSB
0
I
2
C slave address byte
All information provided in this document is subject to legal disclaimers.
SS
2
6
1
which defines the hardware subaddress 0. In multiple device
C-bus master receiver. The only data output from the PCF8576D are
2
C-bus master which is followed by one of two possible PCF8576D
Rev. 13 — 10 May 2012
2
C-bus slave address byte is shown in
2
C-bus slave receiver. It does not initiate I
5
1
2
C-bus slave address have the same hardware
Figure
4
1
18. The sequence is initiated with a START
SS
Universal LCD driver for low multiplex rates
or V
DD
SS
3
0
using a binary coding scheme, so that
for logic 0 and V
2
0
Table
PCF8576D
DD
16.
2
2
1
SA0
for logic 1).
C-bus transfers or
C-bus transfer is
© NXP B.V. 2012. All rights reserved.
2
C-bus:
0
LSB
R/W
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