PCF8576DT/S400/2,1 NXP Semiconductors, PCF8576DT/S400/2,1 Datasheet - Page 21

• Manufacturer Part Number: PCF8576DT/S400/2,1
• Description: LCD Drivers 2.64KHz 50mA 400mW
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT/S400/2,1

• Rohs: yes
• Maximum Clock Frequency: 2.64 kHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Package / Case: TSSOP-56
• Maximum Power Dissipation: 400 mW
• Maximum Supply Current: 50 mA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2000

NXP Semiconductors
PCF8576D
Product data sheet
7.10.1 Data pointer
7.10.2 Subaddress counter
7.10.3 RAM writing in 1:3 multiplex drive mode
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in
pointer is automatically incremented by a value dependent on the selected LCD drive
mode:
If an I
Consequently, the data pointer must be rewritten prior to further RAM accesses.
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see
and the hardware subaddress do not match then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576D occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on the
I
In 1:3 multiplex drive mode, the RAM is written as shown in
well).
Table 6.
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
0
1
2
3
2
•
•
•
•
C-bus interface.
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
2
C-bus data access terminates early then the state of the data pointer is unknown.
Standard RAM filling in 1:3 multiplex drive mode
All information provided in this document is subject to legal disclaimers.
Display RAM addresses (columns)/segment outputs (Sn)
0
a7
a6
a5
-
Rev. 13 — 10 May 2012
1
a4
a3
a2
-
Figure
2
a1
a0
-
-
13. After each byte is stored, the content of the data
Table
3
b7
b6
b5
-
13). If the content of the subaddress counter
Universal LCD driver for low multiplex rates
4
b4
b3
b2
-
-
5
b1
b0
-
Table
6
c7
c6
c5
-
12). Following this command,
Table 6
7
c4
c3
c2
-
PCF8576D
(see
8
c1
c0
-
-
© NXP B.V. 2012. All rights reserved.
Figure 13
9
d7
d6
d5
-
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as
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