PCF8576DT/S400/2,1 NXP Semiconductors, PCF8576DT/S400/2,1 Datasheet - Page 36

• Manufacturer Part Number: PCF8576DT/S400/2,1
• Description: LCD Drivers 2.64KHz 50mA 400mW
• Manufacturer: NXP Semiconductors

Specifications of PCF8576DT/S400/2,1

• Rohs: yes
• Maximum Clock Frequency: 2.64 kHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Package / Case: TSSOP-56
• Maximum Power Dissipation: 400 mW
• Maximum Supply Current: 50 mA
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 2000

NXP Semiconductors
13. Application information
PCF8576D
Product data sheet
13.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the same
I
programmable I
Table 20.
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from
only one device in the cascade to be shared. This arrangement is cost-effective in large
LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other cascaded
PCF8576Ds contribute additional segment outputs but their backplane outputs are left
open-circuit (see
All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal.
This synchronization is guaranteed after the power-on reset. The only time that SYNC is
likely to be needed is if synchronization is lost accidentally, for example, by noise in
adverse electrical environments, or if the LCD multiplex drive mode is changed in an
application using several cascaded PCF8576Ds, as the drive mode cannot be changed
on all of the cascaded devices simultaneously. SYNC can be either an input or an output
signal; a SYNC output is implemented as an open-drain driver with an internal pull-up
resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and
monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored
by the first PCF8576D to assert SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for each LCD drive mode is shown in
Cluster
1
2
2
C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
Addressing cascaded PCF8576D
Bit SA0
0
1
All information provided in this document is subject to legal disclaimers.
2
C-bus slave address (SA0).
Figure
Rev. 13 — 10 May 2012
23).
Pin A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Universal LCD driver for low multiplex rates
Pin A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Pin A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PCF8576D
Figure
© NXP B.V. 2012. All rights reserved.
Device
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
24.
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