MCIMX6L3DVN10AA Freescale Semiconductor, MCIMX6L3DVN10AA Datasheet - Page 13

• Manufacturer Part Number: MCIMX6L3DVN10AA
• Description: Processors - Application Specialized i.MX6 Megrez
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6L3DVN10AA

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-432
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: 0 C
• Number Of Timers: 2

Freescale Semiconductor
TEMPMON
Mnemonic
USBOH2A
TZASC
UART-1
UART-2
UART-3
UART-4
UART-5
SPDIF
SPDC
Block
SSI-1
SSI-2
SSI-3
2x USB 2.0 High
Speed OTG and
Digital Interface
Address Space
UART Interface
Electrophoretic
I2S/SSI/AC97
Block Name
Sony Phillips
Temperature
1x HS Hosts
Trust-Zone
Controller
Controller
Interface
Monitor
Display
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Table 2. i.MX 6SoloLite Modules List (continued)
Connectivity
Connectivity
Connectivity
Subsystem
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Peripherals
Multimedia
Security
System
Control
The SPDC is a feature-rich, low power, and high-performance direct-drive,
active matrix EPD controller. It is specifically designed to drive SiPix™ EPD
panels, supporting a wide variety of TFT backplanes.
A standard audio file transfer format, developed jointly by the Sony and
Phillips corporations. Has Transmitter and Receiver functionality.
The SSI is a full-duplex synchronous interface, which is used on the AP to
provide connectivity with off-chip audio peripherals. The SSI supports a wide
variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up
to 24 bits per word), and clock / frame sync options.
The SSI has two pairs of 8x24 FIFOs and hardware support for an external
DMA controller in order to minimize its impact on system performance. The
second pair of FIFOs provides hardware interleaving of a second audio
stream that reduces CPU overhead in use cases where two time slots are
being used simultaneously.
The temperature monitor/sensor IP, for detecting high temperature conditions.
The Temperature sensor IP for detecting die temperature. The temperature
read out does not reflect case or ambient temperature, but the proximity of the
temperature sensor location on the die. Temperature distribution may not be
uniformly distributed, therefore the read out value may not be the reflection of
the temperature value of the entire die.
The TZASC (TZC-380 by ARM) provides security address region control
functions required for intended application. It is used on the path to the DRAM
controller.
Each of the UARTv2 modules support the following serial data
transmit/receive protocols and configurations:
USBO2H contains:
• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or
• Programmable baud rates up to 4 MHz. This is a higher max baud rate
• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
• IrDA 1.0 support (up to SIR speed of 115200 bps)
• Option to operate as 8-pins full UART, DCE, or DTE
• One Two high-speed OTG module with integrated HS USB PHY
• One identical high-speed Host modules connected to HSIC USB ports.
none)
relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard
and the i.MX31 UART modules.
Brief Description
Modules List
13