MCIMX6L3DVN10AA Freescale Semiconductor, MCIMX6L3DVN10AA Datasheet - Page 70

• Manufacturer Part Number: MCIMX6L3DVN10AA
• Description: Processors - Application Specialized i.MX6 Megrez
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6L3DVN10AA

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-432
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: 0 C
• Number Of Timers: 2

Electrical Characteristics
4.10.5.2 MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TX_DATA3,2,1,0, FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
Table 53
diagram for the values listed in
70
1
2
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
Test conditions: 25pF on each output signal.
Num
M5
M6
M7
M8
FEC_RX_DATA3,2,1,0
FEC_RX_CLK (input)
lists MII transmit channel timing parameters.
FEC_TX_CLK to FEC_TX_DATA3,2,1,0, FEC_TX_EN, FEC_TX_ER
invalid
FEC_TX_CLK to FEC_TX_DATA3,2,1,0, FEC_TX_EN, FEC_TX_ER
valid
FEC_TX_CLK pulse width high
FEC_TX_CLK pulse width low
FEC_RX_ER
FEC_RX_DV
(inputs)
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Figure 36. MII Receive Signal Timing Diagram
Characteristic
Table
Table 53. MII Transmit Signal Timing
53.
M1
1 2
M2
M3
Figure 37
shows MII transmit signal timing
35%
35%
Min
—
M4
5
Max
65%
65%
20
—
Freescale Semiconductor
FEC_TX_CLK period
FEC_TX_CLK period
Unit
ns
ns