MCIMX6L3DVN10AA Freescale Semiconductor, MCIMX6L3DVN10AA Datasheet - Page 25

• Manufacturer Part Number: MCIMX6L3DVN10AA
• Description: Processors - Application Specialized i.MX6 Megrez
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6L3DVN10AA

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-432
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: 0 C
• Number Of Timers: 2

1
Freescale Semiconductor
Deep Sleep Mode
The typical values shown here are for information only and are not guaranteed. These values are average values measured
on a worst-case wafer at 25°C.
STOP_OFF
STOP_ON
STANDBY
(DSM)
• ARM LDO set to 0.9 V
• SoC and PU LDOs set to 1.225 V
• HIGH LDO set to 2.5 V
• PLLs disabled
• DDR is in self refresh
• ARM LDO set to 0.9 V
• SoC LDO set to 1.225 V
• PU LDO is power gated
• HIGH LDO set to 2.5 V
• PLLs disabled
• DDR is in self refresh
• ARM and PU LDOs are power gated
• SoC LDO is in bypass
• HIGH LDO is set to 2.5 V
• PLLs are disabled
• Low voltage
• Well Bias ON
• XTAL is enabled
• ARM and PU LDOs are power gated
• SoC LDO is in bypass
• HIGH LDO is set to 2.5 V
• PLLs are disabled
• Low voltage
• Well Bias ON
• XTAL and bandgap are disabled
Table 12. Stop Mode Current and Power Consumption (continued)
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
VDD_ARM_IN (1.375 V)
VDD_ARM_IN (1.375 V)
VDD_SOC_IN (1.375 V)
VDD_SOC_IN (1.375 V)
VDD_PU_IN (1.375 V)
VDD_HIGH_IN (3.0 V)
VDD_PU_IN (1.375 V)
VDD_HIGH_IN (3.0 V)
VDD_HIGH_IN (3.0 V)
VDD_HIGH_IN (3.0 V)
VDD_ARM_IN (0.9 V)
VDD_ARM_IN (0.9 V)
VDD_SoC_IN (0.9 V)
VDD_SoC_IN (0.9 V)
VDD_PU_IN (0.9 V)
VDD_PU_IN (0.9 V)
Total
Total
Total
Total
Electrical Characteristics
29.3
25.9
10.1
0.75
0.15
2.5
7.5
1.5
4.5
2.5
7.5
0.1
4.0
0.1
1.0
0.1
0.1
0.1
1.3
3
mW
mW
mW
mW
mA
mA
mA
mA
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