MCIMX6L3DVN10AA Freescale Semiconductor, MCIMX6L3DVN10AA Datasheet - Page 83

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MCIMX6L3DVN10AA

Manufacturer Part Number
MCIMX6L3DVN10AA
Description
Processors - Application Specialized i.MX6 Megrez
Manufacturer
Freescale Semiconductor
Type
Multimedia Applicationsr
Datasheet

Specifications of MCIMX6L3DVN10AA

Rohs
yes
Core
ARM Cortex A9
Processor Series
i.MX6
Data Bus Width
32 bit
Maximum Clock Frequency
1 GHz
Data Ram Size
128 KB
Maximum Operating Temperature
+ 95 C
Mounting Style
SMD/SMT
Package / Case
MAPBGA-432
Interface Type
I2C, I2S, UART, USB
Memory Type
L1/L2 Cache, ROM, SRAM
Minimum Operating Temperature
0 C
Number Of Timers
2
Freescale Semiconductor
SS47
SS48
SS49
SS50
SS51
ID
Oversampling clock period
Oversampling clock high period
Oversampling clock rise time
Oversampling clock low period
Oversampling clock fall time
All the timings for the SSI are given for a non-inverted serial clock
polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal
STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables
and in the figures.
All timings are on Audiomux Pads when SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
The terms, WL and BL, refer to Word Length (WL) and Bit Length
(BL).
For internal Frame Sync operation using external clock, the FS timing is
same as that of Tx Data (for example, during AC97 mode of operation).
i.MX 6SoloLite Applications Processors for Consumer Products, Rev. 1
Table 63. SSI Receiver Timing with Internal Clock (continued)
Parameter
NOTE
15.04
Min
6.0
6.0
Electrical Characteristics
Max
3.0
3.0
Unit
ns
ns
ns
ns
ns
83

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