MCIMX6U5EVM10AB Freescale Semiconductor, MCIMX6U5EVM10AB Datasheet - Page 107

• Manufacturer Part Number: MCIMX6U5EVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5EVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 20 C
• Number Of Timers: 2

Table 68
Freescale Semiconductor
IP5
IP6
IP7
IP8
IP9
IP10
IP12
IP13
IP14
IP15
ID
Display interface clock period
Display pixel clock period
Screen width time
HSYNC width time
Horizontal blank interval 1
Horizontal blank interval 2
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
shows timing characteristics of signals presented in
Table 68. Synchronous Display Interface Timing Characteristics (Pixel Level)
Parameter
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
Symbol
Tdpcp
Thbi2
Tdicp
Thsw
Thbi1
Tvbi1
Tvbi2
Tvsw
Tsw
Tsh
DISP_CLK_PER_PIXEL
(SCREEN_HEIGHT -
BGXP - FW)
(SCREEN_HEIGHT)
(SCREEN_WIDTH -
(SCREEN_WIDTH)
BGYP - FH)
(HSYNC_WIDTH)
VSYNC_WIDTH
BGXP
BGYP
×
×
×
Value
Tdicp
Tdicp
(
Tsw
1
×
)
×
Tdicp
×
Tsw
×
Tdicp
Tsw
Figure 66
Display interface clock.
Time of translation of one pixel to display,
DISP_CLK_PER_PIXEL—number of pixel
components in one pixel (1.n). The
DISP_CLK_PER_PIXEL is virtual
parameter to define Display pixel clock
period.
The DISP_CLK_PER_PIXEL is received by
DC/DI one access division to n
components.
SCREEN_WIDTH—screen width in,
interface clocks. horizontal blanking
included.
The SCREEN_WIDTH should be built by
suitable DI’s counter
HSYNC_WIDTH—Hsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter.
BGXP—width of a horizontal blanking
before a first active data in a line (in
interface clocks). The BGXP should be built
by suitable DI’s counter.
Width a horizontal blanking after a last
active data in a line (in interface clocks)
FW—with of active line in interface clocks.
The FW should be built by suitable DI’s
counter.
SCREEN_HEIGHT— screen height in lines
with blanking.
The SCREEN_HEIGHT is a distance
between 2 VSYNCs.
The SCREEN_HEIGHT should be built by
suitable DI’s counter.
VSYNC_WIDTH—Vsync width in DI_CLK
with 0.5 DI_CLK resolution. Defined by DI’s
counter
BGYP—width of first Vertical
blanking interval in line. The BGYP should
be built by suitable DI’s counter.
Width of second Vertical
blanking interval in line. The FH should be
built by suitable DI’s counter.
and
Figure
Description
2
.
Electrical Characteristics
IPP_DISP_CLK
67.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
107