MCIMX6U5EVM10AB Freescale Semiconductor, MCIMX6U5EVM10AB Datasheet - Page 124

• Manufacturer Part Number: MCIMX6U5EVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5EVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 128 KB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: MAPBGA-624
• Interface Type: I2C, I2S, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM
• Minimum Operating Temperature: - 20 C
• Number Of Timers: 2

Electrical Characteristics
4.11.18 SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in
124
(Output)
STCLK
(Input)
SRCK
•
•
AUDMUX port 1
AUDMUX port 2
AUDMUX port 3
AUDMUX port 4
AUDMUX port 5
AUDMUX port 6
AUDMUX port 7
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
The terms WL and BL used in the timing diagrams and tables see Word
Length (WL) and Bit Length (BL).
The SSI timing diagrams use generic signal names wherein the names
used in the i.MX 6Solo/6DualLite Reference Manual (IMX6SDLRM)are
channel specific signal names. For example, a channel clock referenced
in the IOMUXC chapter as AUD3_TXC appears in the timing diagram
as RGMII_TXC.
Port
Signal Nomenclature
Table 77. AUDMUX Port Allocation
Figure 90. STCLK Timing Diagram
Figure 89. SRCK Timing Diagram
AUD3
AUD4
AUD5
AUD6
SSI 1
SSI 2
SSI 3
stclkpl
srckpl
Table
V
V
M
M
77.
NOTE
Internal
Internal
External— AUD3 I/O
External— EIM or CSPI1 I/O through IOMUXC
External— EIM or SD1 I/O through IOMUXC
External— EIM or DISP2 through IOMUXC
Internal
stclkp
srckp
Type and Access
stclkph
srckph
V
V
M
M
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